add all existing files, imported from 5.1, design check violations all fixed, holes of HTCC-AB01 enlarged

This commit is contained in:
Joerg Lehmann 2024-07-13 22:55:02 +02:00
commit 43e0ce9d95
42 changed files with 141969 additions and 0 deletions

View File

@ -0,0 +1,424 @@
(footprint "HTCC-AB01"
(version 20240108)
(generator "pcbnew")
(generator_version "8.0")
(layer "F.Cu")
(descr "HTCC-AB01")
(tags "HTCC-AB01")
(property "Reference" ">NAME"
(at -15.24 -15.24 0)
(layer "F.SilkS")
(uuid "132ef8ee-1963-4b87-a6fb-d3d9966bb03f")
(effects
(font
(size 0.6096 0.6096)
(thickness 0.127)
)
)
)
(property "Value" ">VALUE"
(at 0 22.86 0)
(layer "F.SilkS")
(uuid "b5e49fb1-cf1a-4552-b9cf-fd219663839d")
(effects
(font
(size 0.6096 0.6096)
(thickness 0.127)
)
)
)
(property "Footprint" ""
(at 0 0 0)
(layer "F.Fab")
(hide yes)
(uuid "41ce9017-ad49-496b-959c-7411b2bc5411")
(effects
(font
(size 1.27 1.27)
(thickness 0.15)
)
)
)
(property "Datasheet" ""
(at 0 0 0)
(layer "F.Fab")
(hide yes)
(uuid "c2ce2a47-da26-4b4e-b81b-cdea69d7698b")
(effects
(font
(size 1.27 1.27)
(thickness 0.15)
)
)
)
(property "Description" ""
(at 0 0 0)
(layer "F.Fab")
(hide yes)
(uuid "47b277e8-beea-4b2b-b946-92da0c1179e7")
(effects
(font
(size 1.27 1.27)
(thickness 0.15)
)
)
)
(attr exclude_from_pos_files exclude_from_bom)
(fp_line
(start -11.43 -20.32)
(end -11.43 20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "9c7c83d5-f688-46e1-8064-aadc470ae983")
)
(fp_line
(start -11.43 20.32)
(end 11.43 20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "18a44f51-4b7c-48b1-80bd-e380aa6e85f5")
)
(fp_line
(start -5.08 -20.32)
(end -11.43 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "bb043cbb-0111-412e-8665-c205fe725fde")
)
(fp_line
(start -5.08 0)
(end -5.08 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "d7de9e55-bc3f-4d09-a94f-30be437d703e")
)
(fp_line
(start 5.08 -20.32)
(end 5.08 0)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "e282cd66-0ae4-41f1-8a2a-1c8ec39d0835")
)
(fp_line
(start 5.08 0)
(end -5.08 0)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "fa69a9e8-c421-44d8-a135-75ae958d04a3")
)
(fp_line
(start 11.43 -20.32)
(end 5.08 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "1a9438f0-2c47-4fe8-833f-437dd7702a2e")
)
(fp_line
(start 11.43 20.32)
(end 11.43 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "F.SilkS")
(uuid "bd395e5b-8e1f-4777-943b-aeb6e314e99f")
)
(fp_line
(start -11.43 -20.32)
(end -11.43 20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "2bb3cbcd-950c-4a57-83b5-f3783adc2066")
)
(fp_line
(start -11.43 20.32)
(end 11.43 20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "0ed2ab18-c52a-4f80-811b-1160dd8f4fce")
)
(fp_line
(start -5.08 -20.32)
(end -11.43 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "36ec2ed6-ea03-441d-9a89-54f9cc90f5da")
)
(fp_line
(start -5.08 -12.7)
(end -5.08 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "b4c090a1-04b8-40f4-a07f-b89f71bf05a1")
)
(fp_line
(start 5.08 -20.32)
(end 5.08 -12.7)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "8bd4b4d5-2fd5-4a93-a2b3-8ab7cdd783ac")
)
(fp_line
(start 5.08 0)
(end -5.08 0)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "5c6579eb-c8f8-4140-86d4-f7de12a770a9")
)
(fp_line
(start 11.43 -20.32)
(end 5.08 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "d89ecd93-7da8-4df6-b436-83777a1a0928")
)
(fp_line
(start 11.43 -20.32)
(end 5.08 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "fc3ba97a-e00c-4260-b0f7-a438c21e9451")
)
(fp_line
(start 11.43 20.32)
(end 11.43 -20.32)
(stroke
(width 0.127)
(type solid)
)
(layer "Dwgs.User")
(uuid "07775ade-e740-4caf-9125-892cce8c34e8")
)
(fp_text user "USB"
(at 0 2.5 0)
(layer "F.SilkS")
(uuid "00522103-ebf5-4be9-b524-1e49197fefdd")
(effects
(font
(size 0.8128 0.8128)
(thickness 0.1524)
)
)
)
(pad "1" thru_hole rect
(at -10.14 -10.16)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "e84034ee-71ff-4595-9495-0a52b72cfd43")
)
(pad "2" thru_hole circle
(at -10.14 -7.62)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "f9fde6e9-e045-4989-9f1c-0a5f0cc32a28")
)
(pad "3" thru_hole circle
(at -10.14 -5.08)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "ae59a777-4a14-4253-97cf-efbaaf23dc88")
)
(pad "4" thru_hole circle
(at -10.14 -2.54)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "d0e1b7f5-e393-4371-acc4-8b21a3a0cec6")
)
(pad "5" thru_hole circle
(at -10.16 0)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "46f9fc79-2b98-4850-8db7-fdb2d6517edf")
)
(pad "6" thru_hole circle
(at -10.16 2.54)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "f24ed361-d3b3-45c8-aa17-9a8dc5870bc5")
)
(pad "7" thru_hole circle
(at -10.16 5.08)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "a196189f-acce-477a-a0bb-ea0250fe6069")
)
(pad "8" thru_hole circle
(at -10.16 7.62)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "555bb417-019f-4d75-b1bd-ffed205d800c")
)
(pad "9" thru_hole circle
(at -10.16 10.16)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "681aa22c-aafd-4ca3-9ea3-745cd46d5974")
)
(pad "10" thru_hole circle
(at -10.16 12.7)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "1f368207-8ee2-4987-93c8-66084fd76adc")
)
(pad "11" thru_hole circle
(at -10.16 15.24)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "632e7559-3c67-47a8-b1ed-675d1f96a8db")
)
(pad "12" thru_hole circle
(at 10.14 15.24)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "751c39ae-4506-4b09-bfc7-8e3acd15264b")
)
(pad "13" thru_hole circle
(at 10.14 12.7)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "9b57d381-8c73-4825-bfc9-3eed79ef2c56")
)
(pad "14" thru_hole circle
(at 10.14 10.16)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "d33d3f08-b591-4afd-8739-ee71f9d05d2e")
)
(pad "15" thru_hole circle
(at 10.14 7.62)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "1f8dbdf8-1c8e-477f-a120-ee226a91d420")
)
(pad "16" thru_hole circle
(at 10.14 5.08)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "d322ddbb-694f-461a-a53e-a3af051c8d5b")
)
(pad "17" thru_hole circle
(at 10.14 2.54)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "58a74949-abcd-4673-8442-8521c5cb4b2f")
)
(pad "18" thru_hole circle
(at 10.14 0)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "24cc7936-63b9-4e9d-82ed-bc309cddaede")
)
(pad "19" thru_hole circle
(at 10.14 -2.54)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "2ea00233-a725-4e3b-b5ad-f96dc11b4e2a")
)
(pad "20" thru_hole circle
(at 10.14 -5.08)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "445eea31-c576-48e5-850d-4108c12ce2f3")
)
(pad "21" thru_hole circle
(at 10.14 -7.62)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "1d045423-eebb-4aa7-8b92-9600eb461f8a")
)
(pad "22" thru_hole circle
(at 10.14 -10.16)
(size 1.8 1.8)
(drill 1)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(uuid "d7978584-aa3e-4a7a-b265-6a4fa9d417f6")
)
)

View File

@ -0,0 +1,111 @@
(module IND_LPS4012-103MRB (layer F.Cu) (tedit 5F3EA697)
(descr "")
(fp_text reference REF** (at 0.635 -3.175 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_text value IND_LPS4012-103MRB (at 8.89 3.175 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_poly
(pts
(xy 2.2 -1.395)
(xy 1.65 -1.945)
(xy 0.75 -1.945)
(xy 0.75 -1.17)
(xy 1.33 -0.575)
(xy 1.33 0.575)
(xy 0.75 1.17)
(xy 0.75 1.945)
(xy 1.64 1.945)
(xy 2.2 1.395)
) (layer F.Cu) (width 0.0001)
)
(fp_poly
(pts
(xy -2.2 -1.395)
(xy -1.65 -1.945)
(xy -0.75 -1.945)
(xy -0.75 -1.17)
(xy -1.33 -0.575)
(xy -1.33 0.575)
(xy -0.75 1.17)
(xy -0.75 1.945)
(xy -1.64 1.945)
(xy -2.2 1.395)
) (layer F.Cu) (width 0.0001)
)
(fp_poly
(pts
(xy 2.2 -1.395)
(xy 1.65 -1.945)
(xy 0.75 -1.945)
(xy 0.75 -1.155)
(xy 1.33 -0.575)
(xy 1.33 0.59)
(xy 0.75 1.17)
(xy 0.75 1.945)
(xy 1.65 1.945)
(xy 2.2 1.395)
) (layer F.Paste) (width 0.0001)
)
(fp_poly
(pts
(xy -2.2 -1.395)
(xy -1.65 -1.945)
(xy -0.75 -1.945)
(xy -0.75 -1.155)
(xy -1.33 -0.575)
(xy -1.33 0.59)
(xy -0.75 1.17)
(xy -0.75 1.945)
(xy -1.65 1.945)
(xy -2.2 1.395)
) (layer F.Paste) (width 0.0001)
)
(fp_poly
(pts
(xy -0.65 -2.05)
(xy -1.65 -2.05)
(xy -1.7 -2.05)
(xy -2.3 -1.45)
(xy -2.3 1.45)
(xy -1.7 2.05)
(xy -0.65 2.05)
(xy -0.65 1.1)
(xy -1.2 0.55)
(xy -1.2 -0.55)
(xy -0.65 -1.1)
) (layer F.Mask) (width 0.0001)
)
(fp_poly
(pts
(xy 0.65 -2.05)
(xy 1.7 -2.05)
(xy 2.3 -1.45)
(xy 2.3 1.45)
(xy 1.7 2.05)
(xy 0.65 2.05)
(xy 0.65 1.1)
(xy 1.2 0.55)
(xy 1.2 -0.55)
(xy 0.65 -1.1)
) (layer F.Mask) (width 0.0001)
)
(fp_line (start -1.45 -1.95) (end 1.45 -1.95) (layer F.Fab) (width 0.127))
(fp_line (start 1.95 -1.45) (end 1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.45 1.95) (end 1.45 1.95) (layer F.Fab) (width 0.127))
(fp_line (start -1.95 -1.45) (end -1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.95 -1.45) (end -1.45 -1.95) (layer F.Fab) (width 0.127))
(fp_line (start 1.45 -1.95) (end 1.95 -1.45) (layer F.Fab) (width 0.127))
(fp_line (start 1.45 1.95) (end 1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.45 1.95) (end -1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -0.4 -1.95) (end 0.4 -1.95) (layer F.SilkS) (width 0.127))
(fp_line (start -0.4 1.95) (end 0.4 1.95) (layer F.SilkS) (width 0.127))
(fp_line (start -2.45 -2.2) (end 2.45 -2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.45 -2.2) (end 2.45 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.45 2.2) (end -2.45 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.45 2.2) (end -2.45 -2.2) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -1.765 0.0) (size 0.87 1.15) (layers F.Cu))
(pad 2 smd rect (at 1.765 0.0) (size 0.87 1.15) (layers F.Cu))
)

View File

@ -0,0 +1,111 @@
(module IND_LPS4012-103MRB (layer F.Cu) (tedit 5F3EA697)
(descr "")
(fp_text reference REF** (at 0.635 -3.175 0) (layer F.SilkS)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_text value IND_LPS4012-103MRB (at 8.89 3.175 0) (layer F.Fab)
(effects (font (size 1.0 1.0) (thickness 0.015)))
)
(fp_poly
(pts
(xy 2.2 -1.395)
(xy 1.65 -1.945)
(xy 0.75 -1.945)
(xy 0.75 -1.17)
(xy 1.33 -0.575)
(xy 1.33 0.575)
(xy 0.75 1.17)
(xy 0.75 1.945)
(xy 1.64 1.945)
(xy 2.2 1.395)
) (layer F.Cu) (width 0.0001)
)
(fp_poly
(pts
(xy -2.2 -1.395)
(xy -1.65 -1.945)
(xy -0.75 -1.945)
(xy -0.75 -1.17)
(xy -1.33 -0.575)
(xy -1.33 0.575)
(xy -0.75 1.17)
(xy -0.75 1.945)
(xy -1.64 1.945)
(xy -2.2 1.395)
) (layer F.Cu) (width 0.0001)
)
(fp_poly
(pts
(xy 2.2 -1.395)
(xy 1.65 -1.945)
(xy 0.75 -1.945)
(xy 0.75 -1.155)
(xy 1.33 -0.575)
(xy 1.33 0.59)
(xy 0.75 1.17)
(xy 0.75 1.945)
(xy 1.65 1.945)
(xy 2.2 1.395)
) (layer F.Paste) (width 0.0001)
)
(fp_poly
(pts
(xy -2.2 -1.395)
(xy -1.65 -1.945)
(xy -0.75 -1.945)
(xy -0.75 -1.155)
(xy -1.33 -0.575)
(xy -1.33 0.59)
(xy -0.75 1.17)
(xy -0.75 1.945)
(xy -1.65 1.945)
(xy -2.2 1.395)
) (layer F.Paste) (width 0.0001)
)
(fp_poly
(pts
(xy -0.65 -2.05)
(xy -1.65 -2.05)
(xy -1.7 -2.05)
(xy -2.3 -1.45)
(xy -2.3 1.45)
(xy -1.7 2.05)
(xy -0.65 2.05)
(xy -0.65 1.1)
(xy -1.2 0.55)
(xy -1.2 -0.55)
(xy -0.65 -1.1)
) (layer F.Mask) (width 0.0001)
)
(fp_poly
(pts
(xy 0.65 -2.05)
(xy 1.7 -2.05)
(xy 2.3 -1.45)
(xy 2.3 1.45)
(xy 1.7 2.05)
(xy 0.65 2.05)
(xy 0.65 1.1)
(xy 1.2 0.55)
(xy 1.2 -0.55)
(xy 0.65 -1.1)
) (layer F.Mask) (width 0.0001)
)
(fp_line (start -1.45 -1.95) (end 1.45 -1.95) (layer F.Fab) (width 0.127))
(fp_line (start 1.95 -1.45) (end 1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.45 1.95) (end 1.45 1.95) (layer F.Fab) (width 0.127))
(fp_line (start -1.95 -1.45) (end -1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.95 -1.45) (end -1.45 -1.95) (layer F.Fab) (width 0.127))
(fp_line (start 1.45 -1.95) (end 1.95 -1.45) (layer F.Fab) (width 0.127))
(fp_line (start 1.45 1.95) (end 1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -1.45 1.95) (end -1.95 1.45) (layer F.Fab) (width 0.127))
(fp_line (start -0.4 -1.95) (end 0.4 -1.95) (layer F.SilkS) (width 0.127))
(fp_line (start -0.4 1.95) (end 0.4 1.95) (layer F.SilkS) (width 0.127))
(fp_line (start -2.45 -2.2) (end 2.45 -2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.45 -2.2) (end 2.45 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.45 2.2) (end -2.45 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.45 2.2) (end -2.45 -2.2) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -1.765 0.0) (size 0.87 1.15) (layers F.Cu))
(pad 2 smd rect (at 1.765 0.0) (size 0.87 1.15) (layers F.Cu))
)

View File

@ -0,0 +1,28 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# LPS4012-103MRB
#
DEF LPS4012-103MRB L 0 40 N N 1 L N
F0 "L" -400 300 50 H V L BNN
F1 "LPS4012-103MRB" -400 200 50 H V L BNN
F2 "IND_LPS4012-103MRB" 0 0 50 H I L BNN
F3 "1.2mm" 0 0 50 H I L BNN
F4 "Coil Craft" 0 0 50 H I L BNN
F5 "Manufacturer Recommendations" 0 0 50 H I L BNN
F6 "08/01/13" 0 0 50 H I L BNN
DRAW
P 2 0 0 10 -200 0 -300 0 N
P 2 0 0 10 200 0 300 0 N
A -150 0 50 -1 1800 0 0 10 N -200 0 -100 0
A -50 0 50 -1 1800 0 0 10 N -100 0 0 0
A 50 0 50 -1 1800 0 0 10 N 0 0 100 0
A 150 0 50 -1 1800 0 0 10 N 100 0 200 0
X ~ 1 -500 0 200 R 40 40 0 0 P
X ~ 2 500 0 200 L 40 40 0 0 P
ENDDRAW
ENDDEF
#
# End Library

View File

@ -0,0 +1,111 @@
PCBNEW-LibModule-V1
# encoding utf-8
Units mm
$INDEX
IND_LPS4012-103MRB
$EndINDEX
$MODULE IND_LPS4012-103MRB
Po 0 0 0 15 00000000 00000000 ~~
Li IND_LPS4012-103MRB
Cd
Sc 00000000
At SMD
Op 0 0 0
.SolderMask 0
.SolderPaste 0
T0 0 -3.175 1 1 0 0.05 N V 21 "IND_LPS4012-103MRB"
T1 0.635 3.175 1 1 0 0.05 N V 21 "VAL**"
DP 0 0 0 0 10 0.0001 15
Dl 2.2 -1.395
Dl 1.65 -1.945
Dl 0.75 -1.945
Dl 0.75 -1.17
Dl 1.33 -0.575
Dl 1.33 0.575
Dl 0.75 1.17
Dl 0.75 1.945
Dl 1.64 1.945
Dl 2.2 1.395
DP 0 0 0 0 10 0.0001 15
Dl -2.2 -1.395
Dl -1.65 -1.945
Dl -0.75 -1.945
Dl -0.75 -1.17
Dl -1.33 -0.575
Dl -1.33 0.575
Dl -0.75 1.17
Dl -0.75 1.945
Dl -1.64 1.945
Dl -2.2 1.395
DP 0 0 0 0 10 0.0001 19
Dl 2.2 -1.395
Dl 1.65 -1.945
Dl 0.75 -1.945
Dl 0.75 -1.155
Dl 1.33 -0.575
Dl 1.33 0.59
Dl 0.75 1.17
Dl 0.75 1.945
Dl 1.65 1.945
Dl 2.2 1.395
DP 0 0 0 0 10 0.0001 19
Dl -2.2 -1.395
Dl -1.65 -1.945
Dl -0.75 -1.945
Dl -0.75 -1.155
Dl -1.33 -0.575
Dl -1.33 0.59
Dl -0.75 1.17
Dl -0.75 1.945
Dl -1.65 1.945
Dl -2.2 1.395
DP 0 0 0 0 11 0.0001 23
Dl -0.65 -2.05
Dl -1.65 -2.05
Dl -1.7 -2.05
Dl -2.3 -1.45
Dl -2.3 1.45
Dl -1.7 2.05
Dl -0.65 2.05
Dl -0.65 1.1
Dl -1.2 0.55
Dl -1.2 -0.55
Dl -0.65 -1.1
DP 0 0 0 0 10 0.0001 23
Dl 0.65 -2.05
Dl 1.7 -2.05
Dl 2.3 -1.45
Dl 2.3 1.45
Dl 1.7 2.05
Dl 0.65 2.05
Dl 0.65 1.1
Dl 1.2 0.55
Dl 1.2 -0.55
Dl 0.65 -1.1
DS -1.45 -1.95 1.45 -1.95 0.127 27
DS 1.95 -1.45 1.95 1.45 0.127 27
DS -1.45 1.95 1.45 1.95 0.127 27
DS -1.95 -1.45 -1.95 1.45 0.127 27
DS -1.95 -1.45 -1.45 -1.95 0.127 27
DS 1.45 -1.95 1.95 -1.45 0.127 27
DS 1.45 1.95 1.95 1.45 0.127 27
DS -1.45 1.95 -1.95 1.45 0.127 27
DS -0.4 -1.95 0.4 -1.95 0.127 21
DS -0.4 1.95 0.4 1.95 0.127 21
DS -2.45 -2.2 2.45 -2.2 0.05 26
DS 2.45 -2.2 2.45 2.2 0.05 26
DS 2.45 2.2 -2.45 2.2 0.05 26
DS -2.45 2.2 -2.45 -2.2 0.05 26
$PAD
Sh "1" R 0.87 1.15 0 0 0
At SMD N 00888000
Ne 0 ""
Po -1.765 0
$EndPAD
$PAD
Sh "2" R 0.87 1.15 0 0 0
At SMD N 00888000
Ne 0 ""
Po 1.765 0
$EndPAD
$EndMODULE IND_LPS4012-103MRB

View File

@ -0,0 +1 @@
<!DOCTYPE HTML><html lang="en-US"> <head> <meta charset="UTF-8"> <meta http-equiv="refresh" content="0; url=https://www.snapeda.com/about/import/#"> <script type="text/javascript">window.location.href="https://www.snapeda.com/about/import/#" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/about/import/#">link to the import guide</a>. </body></html>

View File

@ -0,0 +1,53 @@
(module HTCC-AB01 (layer F.Cu) (tedit 5F5271B4)
(descr HTCC-AB01)
(tags HTCC-AB01)
(attr virtual)
(fp_text reference >NAME (at -15.24 -15.24) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.127)))
)
(fp_text value >VALUE (at 0 22.86) (layer F.SilkS)
(effects (font (size 0.6096 0.6096) (thickness 0.127)))
)
(fp_line (start 5.08 -12.7) (end -5.08 -12.7) (layer Dwgs.User) (width 0.127))
(fp_line (start 5.08 -20.32) (end 5.08 -12.7) (layer Dwgs.User) (width 0.127))
(fp_line (start -5.08 -20.32) (end -11.43 -20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start 11.43 20.32) (end 11.43 -20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start -11.43 20.32) (end 11.43 20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start -11.43 -20.32) (end -11.43 20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start -5.08 -12.7) (end -5.08 -20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start -11.43 20.32) (end 11.43 20.32) (layer F.SilkS) (width 0.127))
(fp_line (start 11.43 20.32) (end 11.43 -20.32) (layer F.SilkS) (width 0.127))
(fp_line (start -5.08 -20.32) (end -11.43 -20.32) (layer F.SilkS) (width 0.127))
(fp_line (start 5.08 -20.32) (end 5.08 -12.7) (layer F.SilkS) (width 0.127))
(fp_line (start 5.08 -12.7) (end -5.08 -12.7) (layer F.SilkS) (width 0.127))
(fp_line (start -11.43 -20.32) (end -11.43 20.32) (layer F.SilkS) (width 0.127))
(fp_line (start -5.08 -12.7) (end -5.08 -20.32) (layer F.SilkS) (width 0.127))
(fp_text user USB (at -0.1 -11.43) (layer F.SilkS)
(effects (font (size 0.8128 0.8128) (thickness 0.1524)))
)
(fp_line (start 11.43 -20.32) (end 5.08 -20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start 11.43 -20.32) (end 5.08 -20.32) (layer Dwgs.User) (width 0.127))
(fp_line (start 11.43 -20.32) (end 5.08 -20.32) (layer F.SilkS) (width 0.127))
(pad 1 thru_hole rect (at -10.14 -10.16) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -10.14 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -10.14 -5.08) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -10.14 -2.54) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -10.16 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -10.16 2.54) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at -10.16 5.08) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at -10.16 7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -10.16 10.16) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at -10.16 12.7) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at -10.16 15.24) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 22 thru_hole circle (at 10.14 -10.16) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 21 thru_hole circle (at 10.14 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 20 thru_hole circle (at 10.14 -5.08) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at 10.14 -2.54) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at 10.14 0) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at 10.14 2.54) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at 10.14 5.08) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 10.14 7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 10.14 10.16) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at 10.14 12.7) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at 10.14 15.24) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
)

View File

@ -0,0 +1,52 @@
(module SCCS30B106PRB (layer F.Cu) (tedit 5F4E6AC5)
(descr "CP, Axial series, Axial, Horizontal, pin pitch=26mm, , length*diameter=20*10mm^2, Electrolytic Capacitor, , http://www.kemet.com/Lists/ProductCatalog/Attachments/424/KEM_AC102.pdf")
(tags "CP Axial series Axial Horizontal pin pitch 26mm length 20mm diameter 10mm Electrolytic Capacitor")
(fp_text reference REF** (at 13 -6.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10F (at 13 6.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3 -5) (end 3 5) (layer F.Fab) (width 0.1))
(fp_line (start 33 -5) (end 33 5) (layer F.Fab) (width 0.1))
(fp_line (start 3 -5) (end 4.68 -5) (layer F.Fab) (width 0.1))
(fp_line (start 4.68 -5) (end 5.58 -4.1) (layer F.Fab) (width 0.1))
(fp_line (start 5.58 -4.1) (end 6.48 -5) (layer F.Fab) (width 0.1))
(fp_line (start 6.48 -5) (end 33 -5) (layer F.Fab) (width 0.1))
(fp_line (start 3 5) (end 4.68 5) (layer F.Fab) (width 0.1))
(fp_line (start 4.68 5) (end 5.58 4.1) (layer F.Fab) (width 0.1))
(fp_line (start 5.58 4.1) (end 6.48 5) (layer F.Fab) (width 0.1))
(fp_line (start 6.48 5) (end 33 5) (layer F.Fab) (width 0.1))
(fp_line (start 0.7 -2.54) (end 3 -2.54) (layer F.Fab) (width 0.1))
(fp_line (start 0.7 2.54) (end 3 2.54) (layer F.Fab) (width 0.1))
(fp_line (start 4.7 -2.54) (end 6.5 -2.54) (layer F.Fab) (width 0.1))
(fp_line (start 5.6 -3.44) (end 5.6 -1.64) (layer F.Fab) (width 0.1))
(fp_line (start 0.3 -4.4) (end 1.1 -4.4) (layer F.SilkS) (width 0.12))
(fp_line (start 0.7 -4.8) (end 0.7 -4) (layer F.SilkS) (width 0.12))
(fp_line (start 2.88 -5.12) (end 2.88 5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 33.12 -5.12) (end 33.12 5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.88 -5.12) (end 4.68 -5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.68 -5.12) (end 5.58 -4.22) (layer F.SilkS) (width 0.12))
(fp_line (start 5.58 -4.22) (end 6.48 -5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.48 -5.12) (end 33.12 -5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 2.88 5.12) (end 4.68 5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.68 5.12) (end 5.58 4.22) (layer F.SilkS) (width 0.12))
(fp_line (start 5.58 4.22) (end 6.48 5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 6.48 5.12) (end 33.12 5.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 -2.54) (end 2.88 -2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 1.42 2.54) (end 2.86 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start -1.45 -5.25) (end -1.45 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.45 5.25) (end 33.15 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 33.15 5.25) (end 33.15 -5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 33.15 -5.25) (end -1.45 -5.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 13 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 thru_hole oval (at 0.7 2.5) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0.7 -2.5) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Axial_L20.0mm_D10.0mm_P26.00mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

View File

@ -0,0 +1,24 @@
BY ACCESSING OR USING THESE SYMBOLS & FOOTPRINTS ("MODELS"), YOU ARE ACKNOWLEDGING THAT YOU HAVE READ, FULLY UNDERSTAND AND AGREE TO THESE TERMS AND CONDITIONS (the "Agreement"), WHICH CONSTITUTE A BINDING AGREEMENT BETWEEN YOU AND SNAPEDA, INC., ENTERED INTO ON THE DATE OF SUCH OCCURRENCE (the "Effective Date"). IF YOU ARE ACCESSING OR USING THESE FILES ON BEHALF OF AN ENTITY, YOU REPRESENT THAT YOU HAVE THE RIGHT, AUTHORITY, AND CAPACITY TO BIND SUCH ENTITY TO THIS AGREEMENT AND HEREBY DO SO. IF YOU DO NOT AGREE WITH ANY OF THE TERMS OR CONDITIONS OF THIS AGREEMENT, YOU MUST NOT USE ANY PART OF THESE MODELS.
1. Design License
You and your sub-licensees are hereby licensed to design, manufacture, use and distribute, circuit board designs and circuit boards formed by combining Models provided by SnapEDA with other circuit elements of your choosing. You may then convey such combinations under licensing terms of your choice. 
Individual Models remain the intellectual property of SnapEDA, Inc. You shall not (and shall not permit or encourage any third party to) to do any of the following :
(a) sell, assign, lease, lend, rent, issue, sublicense, make available, or otherwise distribute to any third party, or publicly perform, display or communicate, the Models (for example, by uploading Models to another website or software application);
(b) remove, alter, or conceal, any copyright, trademark, or other proprietary rights notice or legend displayed or contained in the individual Models.
For further clarity, once integrated into a schematic design or PCB layout, Models may be modified freely for the purpose of designing a circuit board. 
2. Limitation of Liability
IN NO EVENT WILL SNAPEDA, TE CONNECTIVITY, OR OUR SUBSIDIARIES, AGENTS, SUCCESSORS, THIRD PARTY PROVIDERS, AND/OR ANY OF THE FOREGOING ENTITIES' RESPECTIVE DIRECTORS, OFFICERS, EMPLOYEES, AGENTS, REPRESENTATIVES, CUSTOMERS, SUPPLIERS, OR LICENSORS BE RESPONSIBLE OR LIABLE UNDER, OR OTHERWISE IN CONNECTION WITH THIS AGREEMENT, FOR:
(a) ANY CONSEQUENTIAL, INDIRECT, SPECIAL, INCIDENTAL, OR PUNITIVE DAMAGES;
(b) ANY LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF REVENUE, OR LOSS OF ANTICIPATED SAVINGS;
(c) ANY LOSS OF, OR DAMAGE TO, DATA, REPUTATION, OR GOODWILL; AND/OR
(d) THE COST OF PROCURING ANY SUBSTITUTE GOODS OR SERVICES.
THE COMBINED AGGREGATE LIABILITY OF SNAPEDA AND ALL SNAPEDA CONTENT AFFILIATES UNDER, OR OTHERWISE IN CONNECTION WITH, THIS AGREEMENT SHALL NOT EXCEED THE TOTAL AMOUNT OF FEES RECEIVED BY SNAPEDA FROM YOU IN THE PREVIOUS TWELVE (12) MONTHS. THE FOREGOING EXCLUSIONS AND LIMITATIONS SHALL APPLY: (a) EVEN IF SNAPEDA OR ANY SNAPEDA CONTENT AFFILIATE HAS BEEN ADVISED, OR SHOULD HAVE BEEN AWARE, OF THE POSSIBILITY OF LOSSES, DAMAGES, OR COSTS; (b) EVEN IF ANY REMEDY IN THIS AGREEMENT FAILS OF ITS ESSENTIAL PURPOSE; AND (c) REGARDLESS OF THE THEORY OR BASIS OF LIABILITY (INCLUDING WITHOUT LIMITATION BREACH OF CONTRACT, TORT, NEGLIGENCE, AND STRICT LIABILITY).

View File

@ -0,0 +1,23 @@
(module T4145015051-001 (layer F.Cu) (tedit 5FECA2F1)
(descr "")
(fp_text reference REF** (at -7.40839 -6.85962 0) (layer F.SilkS)
(effects (font (size 0.787952755906 0.787952755906) (thickness 0.015)))
)
(fp_text value T4145015051-001 (at -2.374505 7.252835 0) (layer F.Fab)
(effects (font (size 0.788590551181 0.788590551181) (thickness 0.015)))
)
(fp_line (start 9.65 6.55) (end -9.85 6.55) (layer F.SilkS) (width 0.127))
(fp_line (start -9.85 6.55) (end -9.85 -5.5) (layer F.SilkS) (width 0.127))
(fp_line (start -9.85 -5.5) (end 9.65 -5.5) (layer F.SilkS) (width 0.127))
(fp_line (start 9.65 -5.5) (end 9.65 6.55) (layer F.SilkS) (width 0.127))
(pad P$1 thru_hole circle (at -1.77 -1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
(pad P$2 thru_hole circle (at 1.77 -1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
(pad P$3 thru_hole circle (at -1.77 1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
(pad P$4 thru_hole circle (at 1.77 1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
(pad P$5 thru_hole circle (at 0.0 0.0) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at 7.5 0.0) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at 7.5 4.0) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at -7.5 0.0) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
(pad None np_thru_hole circle (at -7.5 4.0) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
)

View File

@ -0,0 +1,30 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# T4145015051-001
#
DEF T4145015051-001 J 0 40 N Y 1 L N
F0 "J" -300 500 50 H V L BNN
F1 "T4145015051-001" -300 -500 50 H V L BNN
F2 "T4145015051-001" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
DRAW
P 2 0 0 10 -300 400 -300 -300 N
P 2 0 0 10 -300 -300 300 -300 N
P 2 0 0 10 300 -300 300 400 N
P 2 0 0 10 -300 400 -100 400 N
P 2 0 0 10 -100 400 -100 300 N
P 2 0 0 10 -100 300 100 300 N
P 2 0 0 10 100 300 100 400 N
P 2 0 0 10 100 400 300 400 N
X 5 P$5 0 300 300 D 40 40 0 0 B I
X 2 P$2 200 400 200 D 40 40 0 0 B I
X 1 P$1 -200 400 200 D 40 40 0 0 B I
X 3 P$3 200 -300 200 U 40 40 0 0 B I
X 4 P$4 -200 -300 200 U 40 40 0 0 B I
ENDDRAW
ENDDEF
#
# End Library

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1 @@
<!DOCTYPE HTML><html lang="en-US"> <head> <meta charset="UTF-8"> <meta http-equiv="refresh" content="0; url=https://www.snapeda.com/te/#"> <script type="text/javascript">window.location.href="https://www.snapeda.com/te/#" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/te/#">link to the import guide</a>. </body></html>

View File

@ -0,0 +1,5 @@
(page_layout
(setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
(left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
(line (name segm1:Line) (start 0 0) (end 0 0))
)

96608
kicad-files/fp-info-cache Normal file

File diff suppressed because it is too large Load Diff

6
kicad-files/fp-lib-table Normal file
View File

@ -0,0 +1,6 @@
(fp_lib_table
(version 7)
(lib (name "nau7802")(type "KiCad")(uri "${KIPRJMOD}/nau7802.pretty")(options "")(descr ""))
(lib (name "T4145015051-001")(type "KiCad")(uri "${KIPRJMOD}/T4145015051-001")(options "")(descr ""))
(lib (name "HTCC-AB01")(type "KiCad")(uri "${KIPRJMOD}/HTCC-AB01")(options "")(descr ""))
)

View File

@ -0,0 +1,247 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Conn_01x02_Female
#
DEF Connector_Conn_01x02_Female J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Conn_01x02_Female" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
P 2 1 1 6 -50 -100 -20 -100 N
P 2 1 1 6 -50 0 -20 0 N
X Pin_1 1 -200 0 150 R 50 50 1 1 P
X Pin_2 2 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x02
#
DEF Connector_Generic_Conn_01x02 J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Generic_Conn_01x02" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 50 50 -150 1 1 10 f
X Pin_1 1 -200 0 150 R 50 50 1 1 P
X Pin_2 2 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Net-Tie_2
#
DEF Device_Net-Tie_2 NT 0 0 N N 1 F N
F0 "NT" 0 50 50 H V C CNN
F1 "Device_Net-Tie_2" 0 -50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Net*Tie*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 0 50 0 N
X 1 1 -100 0 100 R 50 50 1 1 P
X 2 2 100 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Sensor_BME280
#
DEF Sensor_BME280 U 0 20 Y Y 1 F N
F0 "U" -350 450 50 H V C CNN
F1 "Sensor_BME280" 300 450 50 H V C CNN
F2 "Package_LGA:Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering" 1500 -450 50 H I C CNN
F3 "" 0 -200 50 H I C CNN
$FPLIST
*LGA*2.5x2.5mm*P0.65mm*Clockwise*
$ENDFPLIST
DRAW
S -400 400 400 -400 0 1 10 f
X GND 1 -100 -600 200 U 50 50 1 1 W
X CSB 2 600 -300 200 L 50 50 1 1 I
X SDI 3 600 -100 200 L 50 50 1 1 B
X SCK 4 600 100 200 L 50 50 1 1 I
X SDO 5 600 300 200 L 50 50 1 1 B
X VDDIO 6 -100 600 200 D 50 50 1 1 W
X GND 7 100 -600 200 U 50 50 1 1 W
X VDD 8 100 600 200 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# T4145015051-001_T4145015051-001
#
DEF T4145015051-001_T4145015051-001 J 0 40 N Y 1 L N
F0 "J" -300 500 50 H V L BNN
F1 "T4145015051-001_T4145015051-001" -300 -500 50 H V L BNN
F2 "T4145015051-001" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
DRAW
P 2 0 0 10 -300 -300 300 -300 N
P 2 0 0 10 -300 400 -300 -300 N
P 2 0 0 10 -300 400 -100 400 N
P 2 0 0 10 -100 300 100 300 N
P 2 0 0 10 -100 400 -100 300 N
P 2 0 0 10 100 300 100 400 N
P 2 0 0 10 100 400 300 400 N
P 2 0 0 10 300 -300 300 400 N
X 1 P$1 -200 400 200 D 40 40 0 0 B I
X 2 P$2 200 400 200 D 40 40 0 0 B I
X 3 P$3 200 -300 200 U 40 40 0 0 B I
X 4 P$4 -200 -300 200 U 40 40 0 0 B I
X 5 P$5 0 300 300 D 40 40 0 0 B I
ENDDRAW
ENDDEF
#
# mini-beieli-pcb-cubecell-eagle-import_HTCC-AB01
#
DEF mini-beieli-pcb-cubecell-eagle-import_HTCC-AB01 U? 0 40 Y Y 1 F N
F0 "U?" 1500 -100 50 H V C CNN
F1 "mini-beieli-pcb-cubecell-eagle-import_HTCC-AB01" 750 850 50 V V C CNN
F2 "" 200 900 50 V I C CNN
F3 "" 200 900 50 V I C CNN
DRAW
S 0 0 1600 1750 0 1 0 f
X GND 1 -100 1450 100 R 50 50 0 0 I
X GPIO5 10 -100 550 100 R 50 50 0 0 B
X RST 11 -100 450 100 R 50 50 0 0 I
X ADC 12 1700 450 100 L 50 50 0 0 I
X GPIO1 13 1700 550 100 L 50 50 0 0 B
X GPIO2 14 1700 650 100 L 50 50 0 0 B
X GPIO3 15 1700 750 100 L 50 50 0 0 B
X RX 16 1700 850 100 L 50 50 0 0 I
X TX 17 1700 950 100 L 50 50 0 0 O
X SCK 18 1700 1050 100 L 50 50 0 0 B
X MISO 19 1700 1150 100 L 50 50 0 0 B
X VS 2 -100 1350 100 R 50 50 0 0 I
X MOSI 20 1700 1250 100 L 50 50 0 0 B
X VIN 21 1700 1350 100 L 50 50 0 0 I
X GND 22 1700 1450 100 L 50 50 0 0 I
X VDD 3 -100 1250 100 R 50 50 0 0 I
X VEXT 4 -100 1150 100 R 50 50 0 0 O
X GND 5 -100 1050 100 R 50 50 0 0 O
X SCL 6 -100 950 100 R 50 50 0 0 I
X SDA 7 -100 850 100 R 50 50 0 0 O
X GPIO0 8 -100 750 100 R 50 50 0 0 B
X GPIO4 9 -100 650 100 R 50 50 0 0 B
ENDDRAW
ENDDEF
#
# mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import
#
DEF mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import U 0 40 Y Y 1 L N
F0 "U" -400 430 70 H V L BNN
F1 "mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import" -400 -600 70 H V L BNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 1 0 0 -400 -500 -400 400 N
P 2 1 0 0 -400 400 400 400 N
P 2 1 0 0 400 -500 -400 -500 N
P 2 1 0 0 400 400 400 -500 N
X REFP 1 -500 300 100 R 0 50 1 0 B
X XIN 10 500 -300 100 L 0 50 1 0 B
X XOUT 11 500 -200 100 L 0 50 1 0 B
X DRDY 12 500 -100 100 L 0 50 1 0 B
X SCLK 13 500 0 100 L 0 50 1 0 B
X SDIO 14 500 100 100 L 0 50 1 0 B
X DVDD 15 500 200 100 L 0 50 1 0 B
X AVDD 16 500 300 100 L 0 50 1 0 B
X VIN1N 2 -500 200 100 R 0 50 1 0 B
X VIN1P 3 -500 100 100 R 0 50 1 0 B
X VIN2N 4 -500 0 100 R 0 50 1 0 B
X VIN2P 5 -500 -100 100 R 0 50 1 0 B
X VBG 6 -500 -200 100 R 0 50 1 0 B
X REFN 7 -500 -300 100 R 0 50 1 0 B
X AVSS 8 -500 -400 100 R 0 50 1 0 B
X DVSS 9 500 -400 100 L 0 50 1 0 B
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_PWR_FLAG
#
DEF power_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "power_PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
# power_VS
#
DEF power_VS #PWR 0 0 Y Y 1 F P
F0 "#PWR" -200 -150 50 H I C CNN
F1 "power_VS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 0 0 0 100 N
P 4 0 1 0 30 50 -30 50 0 100 30 50 F
X VS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

View File

@ -0,0 +1,18 @@
EESchema-DOCLIB Version 2.0
#
$CMP HTCC-AB01
D Heltec CubeCell AM01
K ASR6501, AM01, HELTEC
$ENDCMP
#
$CMP HTCC-AM01
D Heltec CubeCell AM01
K ASR6501, AM01, HELTEC
$ENDCMP
#
$CMP HTCC-AM02
D Heltec CubeCell AM02
K ASR6502, AM02, HELTEC
$ENDCMP
#
#End Doc Library

View File

@ -0,0 +1,18 @@
EESchema-DOCLIB Version 2.0
#
$CMP HTCC-AB01
D Heltec CubeCell AM01
K ASR6501, AM01, HELTEC
$ENDCMP
#
$CMP HTCC-AM01
D Heltec CubeCell AM01
K ASR6501, AM01, HELTEC
$ENDCMP
#
$CMP HTCC-AM02
D Heltec CubeCell AM02
K ASR6502, AM02, HELTEC
$ENDCMP
#
#End Doc Library

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,35 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# NAU7802SOIC-Qwiic_Scale-eagle-import
#
DEF NAU7802SOIC-Qwiic_Scale-eagle-import U 0 40 Y Y 1 L N
F0 "U" -400 430 70 H V L BNN
F1 "NAU7802SOIC-Qwiic_Scale-eagle-import" -400 -600 70 H V L BNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 1 0 0 -400 -500 -400 400 N
P 2 1 0 0 -400 400 400 400 N
P 2 1 0 0 400 -500 -400 -500 N
P 2 1 0 0 400 400 400 -500 N
X REFP 1 -500 300 100 R 0 50 1 0 B
X XIN 10 500 -300 100 L 0 50 1 0 B
X XOUT 11 500 -200 100 L 0 50 1 0 B
X DRDY 12 500 -100 100 L 0 50 1 0 B
X SCLK 13 500 0 100 L 0 50 1 0 B
X SDIO 14 500 100 100 L 0 50 1 0 B
X DVDD 15 500 200 100 L 0 50 1 0 B
X AVDD 16 500 300 100 L 0 50 1 0 B
X VIN1N 2 -500 200 100 R 0 50 1 0 B
X VIN1P 3 -500 100 100 R 0 50 1 0 B
X VIN2N 4 -500 0 100 R 0 50 1 0 B
X VIN2P 5 -500 -100 100 R 0 50 1 0 B
X VBG 6 -500 -200 100 R 0 50 1 0 B
X REFN 7 -500 -300 100 R 0 50 1 0 B
X AVSS 8 -500 -400 100 R 0 50 1 0 B
X DVSS 9 500 -400 100 L 0 50 1 0 B
ENDDRAW
ENDDEF
#
#End Library

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,82 @@
{
"board": {
"active_layer": 31,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": false,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
13,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36,
39,
40
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"git": {
"repo_password": "",
"repo_type": "",
"repo_username": "",
"ssh_key": ""
},
"meta": {
"filename": "mini-beieli-pcb-cubecell.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View File

@ -0,0 +1,659 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 1,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.2,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.4,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "mini-beieli-pcb-cubecell.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Default",
"pattern": "/AB_RED"
},
{
"netclass": "Default",
"pattern": "/AGND"
},
{
"netclass": "Default",
"pattern": "/A_GREEN"
},
{
"netclass": "Default",
"pattern": "/A_WHITE"
},
{
"netclass": "Default",
"pattern": "/B_GREEN"
},
{
"netclass": "Default",
"pattern": "/B_WHITE"
},
{
"netclass": "Default",
"pattern": "/GPIO0"
},
{
"netclass": "Default",
"pattern": "/SCL"
},
{
"netclass": "Default",
"pattern": "/SDA"
},
{
"netclass": "Default",
"pattern": "/VEXT"
},
{
"netclass": "Default",
"pattern": "GND"
},
{
"netclass": "Default",
"pattern": "Net-(C4-Pad1)"
},
{
"netclass": "Default",
"pattern": "Net-(C4-Pad2)"
},
{
"netclass": "Default",
"pattern": "Net-(C5-Pad1)"
},
{
"netclass": "Default",
"pattern": "Net-(J3-Pad1)"
},
{
"netclass": "Default",
"pattern": "Net-(LIPO1-Pad1)"
},
{
"netclass": "Default",
"pattern": "Net-(R1-Pad2)"
},
{
"netclass": "Default",
"pattern": "VS"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"name": "Grouped By Value",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"page_layout_descr_file": "mini_beieli.kicad_wks",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"e46353ff-c98e-48ad-9837-e1778144e38b",
"Root"
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,43 @@
update=Sa 05 Sep 2020 11:51:39
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=mini_beieli.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

View File

@ -0,0 +1,626 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 1
Title "mini-beieli-pcb-cubecell"
Date "2020-12-26"
Rev "5.1"
Comp "nbit Informatik GmbH"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Sensor:BME280 U1
U 1 1 5F40DD10
P 9450 7350
F 0 "U1" H 9000 7450 50 0000 R CNN
F 1 "BME280" H 9000 7350 50 0000 R CNN
F 2 "Package_LGA:Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering" H 10950 6900 50 0001 C CNN
F 3 "https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BME280-DS002.pdf" H 9450 7150 50 0001 C CNN
1 9450 7350
1 0 0 -1
$EndComp
$Comp
L mini-beieli-pcb-cubecell-rescue:NAU7802SOIC-Qwiic_Scale-eagle-import U2
U 1 1 5F41501D
P 14100 7250
F 0 "U2" H 13750 7750 70 0000 C CNN
F 1 "NAU7802SOIC" H 14100 6650 70 0000 C CNN
F 2 "nau7802:SOIC127P700X210-16N" H 14100 7250 50 0001 C CNN
F 3 "" H 14100 7250 50 0001 C CNN
1 14100 7250
1 0 0 -1
$EndComp
Wire Wire Line
7000 0 8150 0
$Comp
L power:GND #PWR0105
U 1 1 5F5682D4
P 3000 3100
F 0 "#PWR0105" H 3000 2850 50 0001 C CNN
F 1 "GND" V 3000 2950 50 0000 R CNN
F 2 "" H 3000 3100 50 0001 C CNN
F 3 "" H 3000 3100 50 0001 C CNN
1 3000 3100
1 0 0 -1
$EndComp
Text Label 10500 7250 0 50 ~ 0
SCL
Wire Wire Line
10050 7250 10500 7250
Text Label 10500 7450 0 50 ~ 0
SDA
Wire Wire Line
10050 7450 10500 7450
$Comp
L Device:R R1
U 1 1 5F6AF340
P 10250 6800
F 0 "R1" H 10350 6850 50 0000 L CNN
F 1 "10k" H 10350 6750 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 10180 6800 50 0001 C CNN
F 3 "~" H 10250 6800 50 0001 C CNN
1 10250 6800
1 0 0 -1
$EndComp
Wire Wire Line
10250 6550 10250 6650
Wire Wire Line
10050 7050 10250 7050
Wire Wire Line
10250 7050 10250 6950
Text Label 14950 7150 0 50 ~ 0
SDA
Wire Wire Line
14600 7150 14950 7150
Text Label 14950 7250 0 50 ~ 0
SCL
Wire Wire Line
14600 7250 14950 7250
Text Label 14950 7350 0 50 ~ 0
GPIO0
Wire Wire Line
14600 7350 14950 7350
NoConn ~ 14600 7450
NoConn ~ 14600 7550
Wire Wire Line
14600 7650 14950 7650
Wire Wire Line
13600 7550 13450 7550
Wire Wire Line
13450 7550 13450 7650
Connection ~ 13450 7650
Wire Wire Line
13450 7650 13600 7650
$Comp
L Device:C C5
U 1 1 5F720CB8
P 12950 7600
F 0 "C5" H 13100 7650 50 0000 L CNN
F 1 "0.1uF" H 13100 7550 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 12988 7450 50 0001 C CNN
F 3 "~" H 12950 7600 50 0001 C CNN
1 12950 7600
1 0 0 -1
$EndComp
Wire Wire Line
12950 7450 13600 7450
Wire Wire Line
12950 7750 13450 7750
Wire Wire Line
13450 7750 13450 7650
$Comp
L Device:C C4
U 1 1 5F78BFC8
P 13250 7000
F 0 "C4" H 13050 7100 50 0000 L CNN
F 1 "0.1uF" H 12950 7000 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 13288 6850 50 0001 C CNN
F 3 "~" H 13250 7000 50 0001 C CNN
1 13250 7000
1 0 0 -1
$EndComp
Wire Wire Line
13250 7150 13600 7150
Wire Wire Line
13600 7050 13400 7050
Wire Wire Line
13400 7050 13400 6850
Wire Wire Line
13400 6850 13250 6850
Wire Wire Line
14600 6950 14950 6950
Wire Wire Line
14950 6950 14950 6400
$Comp
L Device:C C3
U 1 1 5F7C8E30
P 14150 6550
F 0 "C3" H 13900 6600 50 0000 L CNN
F 1 "1uF" H 13850 6500 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 14188 6400 50 0001 C CNN
F 3 "~" H 14150 6550 50 0001 C CNN
1 14150 6550
1 0 0 -1
$EndComp
Connection ~ 14150 6400
Wire Wire Line
14150 6400 14950 6400
Wire Wire Line
12150 6400 12950 6400
Wire Wire Line
13600 6950 13550 6950
Wire Wire Line
13550 6950 13550 6400
Connection ~ 13550 6400
Wire Wire Line
13550 6400 14150 6400
$Comp
L Device:C C2
U 1 1 5F853CE7
P 12950 6550
F 0 "C2" H 13100 6600 50 0000 L CNN
F 1 "0.1uF" H 13100 6500 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 12988 6400 50 0001 C CNN
F 3 "~" H 12950 6550 50 0001 C CNN
1 12950 6550
1 0 0 -1
$EndComp
Connection ~ 12950 6400
Wire Wire Line
12950 6400 13550 6400
$Comp
L Device:R R2
U 1 1 5F860866
P 12750 6850
F 0 "R2" V 12650 6750 50 0000 C CNN
F 1 "47" V 12650 6900 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 12680 6850 50 0001 C CNN
F 3 "~" H 12750 6850 50 0001 C CNN
1 12750 6850
0 1 1 0
$EndComp
Wire Wire Line
12900 6850 13250 6850
Connection ~ 13250 6850
$Comp
L Device:R R3
U 1 1 5F86CB81
P 12750 7150
F 0 "R3" V 12650 7050 50 0000 C CNN
F 1 "47" V 12650 7200 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 12680 7150 50 0001 C CNN
F 3 "~" H 12750 7150 50 0001 C CNN
1 12750 7150
0 1 1 0
$EndComp
Wire Wire Line
12900 7150 13250 7150
Connection ~ 13250 7150
Text Label 12150 6400 0 50 ~ 0
AB_RED
Text Label 12150 6850 0 50 ~ 0
A_WHITE
Wire Wire Line
12150 6850 12600 6850
Text Label 12150 7150 0 50 ~ 0
A_GREEN
Wire Wire Line
12150 7150 12600 7150
$Comp
L Connector:Conn_01x02_Female SOLAR1
U 1 1 5FC3F569
P 9000 2050
F 0 "SOLAR1" H 9050 2050 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 1950 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 2050 50 0001 C CNN
F 3 "~" H 9000 2050 50 0001 C CNN
1 9000 2050
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0123
U 1 1 5FC5B972
P 8050 2150
F 0 "#PWR0123" H 8050 1900 50 0001 C CNN
F 1 "GND" H 8100 1950 50 0000 C CNN
F 2 "" H 8050 2150 50 0001 C CNN
F 3 "" H 8050 2150 50 0001 C CNN
1 8050 2150
1 0 0 -1
$EndComp
Wire Wire Line
8050 2150 8800 2150
$Comp
L Device:Net-Tie_2 NT1
U 1 1 6045DF23
P 14150 8000
F 0 "NT1" H 14150 7800 50 0000 C CNN
F 1 "Net-Tie_2" H 14150 7900 50 0000 C CNN
F 2 "NetTie:NetTie-2_THT_Pad1.0mm" H 14150 8000 50 0001 C CNN
F 3 "~" H 14150 8000 50 0001 C CNN
1 14150 8000
1 0 0 -1
$EndComp
Wire Wire Line
14250 8000 14950 8000
Connection ~ 13450 7750
$Comp
L power:VS #PWR0107
U 1 1 606E613C
P 8050 2050
F 0 "#PWR0107" H 7850 1900 50 0001 C CNN
F 1 "VS" H 8100 2250 50 0000 C CNN
F 2 "" H 8050 2050 50 0001 C CNN
F 3 "" H 8050 2050 50 0001 C CNN
1 8050 2050
1 0 0 -1
$EndComp
Wire Wire Line
13450 7750 13450 8000
Wire Wire Line
14950 7650 14950 8000
Wire Wire Line
12950 6700 13450 6700
Wire Wire Line
13450 8000 14050 8000
Connection ~ 9350 6750
$Comp
L power:GND #PWR0106
U 1 1 612B9B42
P 14950 8000
F 0 "#PWR0106" H 14950 7750 50 0001 C CNN
F 1 "GND" H 15000 7800 50 0000 C CNN
F 2 "" H 14950 8000 50 0001 C CNN
F 3 "" H 14950 8000 50 0001 C CNN
1 14950 8000
1 0 0 -1
$EndComp
Connection ~ 14950 8000
Connection ~ 13450 6700
Wire Wire Line
13450 6700 14150 6700
Connection ~ 13450 7550
Text Label 13450 8000 0 50 ~ 0
AGND
Wire Wire Line
10100 7650 10050 7650
Wire Wire Line
10100 6550 10250 6550
Wire Wire Line
8300 6750 9350 6750
$Comp
L Device:C C1
U 1 1 5FD34EBD
P 8300 7300
F 0 "C1" H 8050 7350 50 0000 L CNN
F 1 "0.1uF" H 7950 7250 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 8338 7150 50 0001 C CNN
F 3 "~" H 8300 7300 50 0001 C CNN
1 8300 7300
1 0 0 -1
$EndComp
Wire Wire Line
8300 7150 8300 6750
Wire Wire Line
8300 7450 8300 7950
Wire Wire Line
9350 7950 9550 7950
Connection ~ 9350 7950
$Comp
L power:GND #PWR0111
U 1 1 61898153
P 8300 7950
F 0 "#PWR0111" H 8300 7700 50 0001 C CNN
F 1 "GND" H 8350 7750 50 0000 C CNN
F 2 "" H 8300 7950 50 0001 C CNN
F 3 "" H 8300 7950 50 0001 C CNN
1 8300 7950
1 0 0 -1
$EndComp
Connection ~ 8300 7950
Wire Wire Line
8300 7950 9350 7950
Wire Wire Line
9350 6750 9550 6750
Wire Wire Line
10100 6750 10100 7650
Wire Wire Line
10100 6550 10100 6750
Connection ~ 10100 6750
Connection ~ 9550 6750
Wire Wire Line
9550 6750 10100 6750
Wire Wire Line
13450 6700 13450 7550
Text Label 12150 8250 0 50 ~ 0
B_WHITE
Text Label 12150 8550 0 50 ~ 0
B_GREEN
Wire Wire Line
13600 7250 12700 7250
Wire Wire Line
12700 7250 12700 8250
Wire Wire Line
12150 8250 12700 8250
Wire Wire Line
12800 7350 13600 7350
Wire Wire Line
12150 8550 12800 8550
Text Label 3300 3000 0 50 ~ 0
SCL
Text Label 3300 3100 0 50 ~ 0
SDA
Text Label 3300 3200 0 50 ~ 0
GPIO0
$Comp
L mini-beieli-pcb-cubecell-eagle-import:HTCC-AB01 HTCC-AB01
U 1 1 5F6D2856
P 3850 3950
F 0 "HTCC-AB01" H 4650 5900 50 0000 C CNN
F 1 "HTCC-AB01" H 4650 5800 50 0000 C CNN
F 2 "SUPERCAP:HTCC-AB01" V 4050 4850 50 0001 C CNN
F 3 "" V 4050 4850 50 0001 C CNN
1 3850 3950
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 5F8B4409
P 5850 2650
F 0 "#PWR0101" H 5850 2400 50 0001 C CNN
F 1 "GND" H 5900 2450 50 0000 C CNN
F 2 "" H 5850 2650 50 0001 C CNN
F 3 "" H 5850 2650 50 0001 C CNN
1 5850 2650
1 0 0 -1
$EndComp
Wire Wire Line
5850 2500 5850 2650
Text Label 3300 2800 0 50 ~ 0
VEXT
Wire Wire Line
3000 2500 3750 2500
Text Label 9350 6450 0 50 ~ 0
VEXT
Wire Wire Line
9350 6450 9350 6750
Text Label 14950 7050 0 50 ~ 0
VEXT
Wire Wire Line
14600 7050 14950 7050
Wire Wire Line
5550 2500 5850 2500
NoConn ~ 5550 2600
NoConn ~ 5550 2700
NoConn ~ 5550 2800
NoConn ~ 5550 2900
NoConn ~ 5550 3000
NoConn ~ 5550 3100
NoConn ~ 5550 3200
NoConn ~ 5550 3300
NoConn ~ 5550 3400
NoConn ~ 5550 3500
Wire Wire Line
3000 2500 3000 2900
Wire Wire Line
3300 2800 3750 2800
Wire Wire Line
3300 3000 3750 3000
Wire Wire Line
3300 3100 3750 3100
Wire Wire Line
3300 3200 3750 3200
NoConn ~ 3750 3300
NoConn ~ 3750 3400
NoConn ~ 3750 3500
Wire Wire Line
3000 2900 3750 2900
Connection ~ 3000 2900
Wire Wire Line
3000 2900 3000 3100
Wire Wire Line
5650 7400 6050 7400
Text Label 6050 7400 0 50 ~ 0
AGND
Wire Wire Line
4900 7200 5050 7200
Wire Wire Line
4900 7300 4900 7200
Wire Wire Line
6050 7300 4900 7300
Text Label 6050 7300 0 50 ~ 0
B_GREEN
Wire Wire Line
4900 7600 5050 7600
Wire Wire Line
4900 7750 4900 7600
Wire Wire Line
6050 7750 4900 7750
Text Label 6050 7750 0 50 ~ 0
B_WHITE
Wire Wire Line
5750 7600 6050 7600
Text Label 6050 7600 0 50 ~ 0
AGND
Wire Wire Line
5750 7200 6050 7200
Text Label 6050 7200 0 50 ~ 0
AB_RED
$Comp
L T4145015051-001:T4145015051-001 J2
U 1 1 602AD758
P 5350 7400
F 0 "J2" V 4850 7450 50 0000 C CNN
F 1 "T4145015051-001" V 4950 7450 50 0000 C CNN
F 2 "T4145015051-001:T4145015051-001" H 5350 7400 50 0001 L BNN
F 3 "Circular Metric Connectors; M12 R/A F PNLREAR STAMPED PIN A-CODE 5P" H 5350 7400 50 0001 L BNN
F 4 "https://www.te.com/usa-en/product-T4145015051-001.html?te_bu=Cor&te_type=disp&te_campaign=seda_glo_cor-seda-global-disp-prtnr-fy19-seda-model-bom-cta_sma-317_1&elqCampaignId=32493" H 5350 7400 50 0001 L BNN "Field4"
F 5 "TE Connectivity" H 5350 7400 50 0001 L BNN "Field5"
F 6 "Unavailable" H 5350 7400 50 0001 L BNN "Field6"
F 7 "None" H 5350 7400 50 0001 L BNN "Field7"
F 8 "T4145015051-001" H 5350 7400 50 0001 L BNN "Field8"
F 9 "T4145015051-001" H 5350 7400 50 0001 L BNN "Field9"
F 10 "None" H 5350 7400 50 0001 L BNN "Field10"
1 5350 7400
0 1 1 0
$EndComp
Wire Wire Line
3600 7400 4000 7400
Text Label 4000 7400 0 50 ~ 0
AGND
Wire Wire Line
2850 7200 3000 7200
Wire Wire Line
2850 7300 2850 7200
Wire Wire Line
4000 7300 2850 7300
Text Label 4000 7300 0 50 ~ 0
A_GREEN
Wire Wire Line
2850 7600 3000 7600
Wire Wire Line
2850 7750 2850 7600
Wire Wire Line
4000 7750 2850 7750
Text Label 4000 7750 0 50 ~ 0
A_WHITE
Wire Wire Line
3700 7600 4000 7600
Text Label 4000 7600 0 50 ~ 0
AGND
Wire Wire Line
3700 7200 4000 7200
Text Label 4000 7200 0 50 ~ 0
AB_RED
$Comp
L T4145015051-001:T4145015051-001 J1
U 1 1 601E2EC5
P 3300 7400
F 0 "J1" V 2800 7450 50 0000 C CNN
F 1 "T4145015051-001" V 2900 7450 50 0000 C CNN
F 2 "T4145015051-001:T4145015051-001" H 3300 7400 50 0001 L BNN
F 3 "Circular Metric Connectors; M12 R/A F PNLREAR STAMPED PIN A-CODE 5P" H 3300 7400 50 0001 L BNN
F 4 "https://www.te.com/usa-en/product-T4145015051-001.html?te_bu=Cor&te_type=disp&te_campaign=seda_glo_cor-seda-global-disp-prtnr-fy19-seda-model-bom-cta_sma-317_1&elqCampaignId=32493" H 3300 7400 50 0001 L BNN "Field4"
F 5 "TE Connectivity" H 3300 7400 50 0001 L BNN "Field5"
F 6 "Unavailable" H 3300 7400 50 0001 L BNN "Field6"
F 7 "None" H 3300 7400 50 0001 L BNN "Field7"
F 8 "T4145015051-001" H 3300 7400 50 0001 L BNN "Field8"
F 9 "T4145015051-001" H 3300 7400 50 0001 L BNN "Field9"
F 10 "None" H 3300 7400 50 0001 L BNN "Field10"
1 3300 7400
0 1 1 0
$EndComp
Text Notes 3500 1550 0 118 ~ 24
CubeCell (MCU/LoraWAN)
Text Notes 8000 1550 0 118 ~ 24
Connectors
Text Notes 3000 6700 0 118 ~ 24
LoadCell Connector
Text Notes 7700 6000 0 118 ~ 24
Temp/Humidity Sensor (BME280)
Text Notes 13000 6000 0 118 ~ 24
ADC (NAU7802)
Wire Wire Line
12800 8550 12800 7350
Text Label 3300 2600 0 50 ~ 0
VS
Wire Wire Line
3300 2600 3750 2600
NoConn ~ 3750 2700
$Comp
L power:PWR_FLAG #FLG0101
U 1 1 5FE71A37
P 8550 2050
F 0 "#FLG0101" H 8550 2125 50 0001 C CNN
F 1 "PWR_FLAG" H 8550 2250 50 0000 C CNN
F 2 "" H 8550 2050 50 0001 C CNN
F 3 "~" H 8550 2050 50 0001 C CNN
1 8550 2050
1 0 0 -1
$EndComp
Connection ~ 8550 2050
Wire Wire Line
8550 2050 8800 2050
Wire Wire Line
8050 2050 8550 2050
Text Notes 8000 1750 0 50 ~ 0
5.5V - 7V
$Comp
L Connector:Conn_01x02_Female SWITCH1
U 1 1 5FE8083E
P 9000 2800
F 0 "SWITCH1" H 9050 2800 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 2700 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 2800 50 0001 C CNN
F 3 "~" H 9000 2800 50 0001 C CNN
1 9000 2800
1 0 0 -1
$EndComp
Wire Wire Line
8050 2900 8800 2900
$Comp
L Connector:Conn_01x02_Female LIPO1
U 1 1 5FE8567F
P 9000 3500
F 0 "LIPO1" H 9050 3500 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 3400 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 3500 50 0001 C CNN
F 3 "~" H 9000 3500 50 0001 C CNN
1 9000 3500
1 0 0 -1
$EndComp
Wire Wire Line
8050 3600 8800 3600
Wire Wire Line
8050 3500 8800 3500
$Comp
L Connector_Generic:Conn_01x02 J3
U 1 1 5FEA044E
P 9200 4300
F 0 "J3" H 9300 4300 50 0000 L CNN
F 1 "Conn_01x02" H 9300 4200 50 0000 L CNN
F 2 "Connector_Wire:SolderWire-0.1sqmm_1x02_P3.6mm_D0.4mm_OD1mm" H 9200 4300 50 0001 C CNN
F 3 "~" H 9200 4300 50 0001 C CNN
1 9200 4300
1 0 0 -1
$EndComp
Text Notes 8900 3450 0 50 ~ 0
+
$Comp
L power:GND #PWR0102
U 1 1 5FEAB739
P 8050 3600
F 0 "#PWR0102" H 8050 3350 50 0001 C CNN
F 1 "GND" H 8100 3400 50 0000 C CNN
F 2 "" H 8050 3600 50 0001 C CNN
F 3 "" H 8050 3600 50 0001 C CNN
1 8050 3600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0103
U 1 1 5FEB0754
P 9000 4400
F 0 "#PWR0103" H 9000 4150 50 0001 C CNN
F 1 "GND" H 9050 4200 50 0000 C CNN
F 2 "" H 9000 4400 50 0001 C CNN
F 3 "" H 9000 4400 50 0001 C CNN
1 9000 4400
1 0 0 -1
$EndComp
Text Notes 9000 4250 0 50 ~ 0
+
Wire Wire Line
9000 4300 7600 4300
Wire Wire Line
7600 4300 7600 2800
Wire Wire Line
7600 2800 8800 2800
Wire Wire Line
8050 2900 8050 3500
$EndSCHEMATC

View File

@ -0,0 +1,626 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 1
Title "mini-beieli-pcb-cubecell"
Date "2020-12-26"
Rev "5.1"
Comp "nbit Informatik GmbH"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Sensor:BME280 U1
U 1 1 5F40DD10
P 9450 7350
F 0 "U1" H 9000 7450 50 0000 R CNN
F 1 "BME280" H 9000 7350 50 0000 R CNN
F 2 "Package_LGA:Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering" H 10950 6900 50 0001 C CNN
F 3 "https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BME280-DS002.pdf" H 9450 7150 50 0001 C CNN
1 9450 7350
1 0 0 -1
$EndComp
$Comp
L mini-beieli-pcb-cubecell-rescue:NAU7802SOIC-Qwiic_Scale-eagle-import U2
U 1 1 5F41501D
P 14100 7250
F 0 "U2" H 13750 7750 70 0000 C CNN
F 1 "NAU7802SOIC" H 14100 6650 70 0000 C CNN
F 2 "nau7802:SOIC127P700X210-16N" H 14100 7250 50 0001 C CNN
F 3 "" H 14100 7250 50 0001 C CNN
1 14100 7250
1 0 0 -1
$EndComp
Wire Wire Line
7000 0 8150 0
$Comp
L power:GND #PWR0105
U 1 1 5F5682D4
P 3000 3100
F 0 "#PWR0105" H 3000 2850 50 0001 C CNN
F 1 "GND" V 3000 2950 50 0000 R CNN
F 2 "" H 3000 3100 50 0001 C CNN
F 3 "" H 3000 3100 50 0001 C CNN
1 3000 3100
1 0 0 -1
$EndComp
Text Label 10500 7250 0 50 ~ 0
SCL
Wire Wire Line
10050 7250 10500 7250
Text Label 10500 7450 0 50 ~ 0
SDA
Wire Wire Line
10050 7450 10500 7450
$Comp
L Device:R R1
U 1 1 5F6AF340
P 10250 6800
F 0 "R1" H 10350 6850 50 0000 L CNN
F 1 "10k" H 10350 6750 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 10180 6800 50 0001 C CNN
F 3 "~" H 10250 6800 50 0001 C CNN
1 10250 6800
1 0 0 -1
$EndComp
Wire Wire Line
10250 6550 10250 6650
Wire Wire Line
10050 7050 10250 7050
Wire Wire Line
10250 7050 10250 6950
Text Label 14950 7150 0 50 ~ 0
SDA
Wire Wire Line
14600 7150 14950 7150
Text Label 14950 7250 0 50 ~ 0
SCL
Wire Wire Line
14600 7250 14950 7250
Text Label 14950 7350 0 50 ~ 0
GPIO0
Wire Wire Line
14600 7350 14950 7350
NoConn ~ 14600 7450
NoConn ~ 14600 7550
Wire Wire Line
14600 7650 14950 7650
Wire Wire Line
13600 7550 13450 7550
Wire Wire Line
13450 7550 13450 7650
Connection ~ 13450 7650
Wire Wire Line
13450 7650 13600 7650
$Comp
L Device:C C5
U 1 1 5F720CB8
P 12950 7600
F 0 "C5" H 13100 7650 50 0000 L CNN
F 1 "0.1uF" H 13100 7550 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 12988 7450 50 0001 C CNN
F 3 "~" H 12950 7600 50 0001 C CNN
1 12950 7600
1 0 0 -1
$EndComp
Wire Wire Line
12950 7450 13600 7450
Wire Wire Line
12950 7750 13450 7750
Wire Wire Line
13450 7750 13450 7650
$Comp
L Device:C C4
U 1 1 5F78BFC8
P 13250 7000
F 0 "C4" H 13050 7100 50 0000 L CNN
F 1 "0.1uF" H 12950 7000 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 13288 6850 50 0001 C CNN
F 3 "~" H 13250 7000 50 0001 C CNN
1 13250 7000
1 0 0 -1
$EndComp
Wire Wire Line
13250 7150 13600 7150
Wire Wire Line
13600 7050 13400 7050
Wire Wire Line
13400 7050 13400 6850
Wire Wire Line
13400 6850 13250 6850
Wire Wire Line
14600 6950 14950 6950
Wire Wire Line
14950 6950 14950 6400
$Comp
L Device:C C3
U 1 1 5F7C8E30
P 14150 6550
F 0 "C3" H 13900 6600 50 0000 L CNN
F 1 "1uF" H 13850 6500 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 14188 6400 50 0001 C CNN
F 3 "~" H 14150 6550 50 0001 C CNN
1 14150 6550
1 0 0 -1
$EndComp
Connection ~ 14150 6400
Wire Wire Line
14150 6400 14950 6400
Wire Wire Line
12150 6400 12950 6400
Wire Wire Line
13600 6950 13550 6950
Wire Wire Line
13550 6950 13550 6400
Connection ~ 13550 6400
Wire Wire Line
13550 6400 14150 6400
$Comp
L Device:C C2
U 1 1 5F853CE7
P 12950 6550
F 0 "C2" H 13100 6600 50 0000 L CNN
F 1 "0.1uF" H 13100 6500 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 12988 6400 50 0001 C CNN
F 3 "~" H 12950 6550 50 0001 C CNN
1 12950 6550
1 0 0 -1
$EndComp
Connection ~ 12950 6400
Wire Wire Line
12950 6400 13550 6400
$Comp
L Device:R R2
U 1 1 5F860866
P 12750 6850
F 0 "R2" V 12650 6750 50 0000 C CNN
F 1 "47" V 12650 6900 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 12680 6850 50 0001 C CNN
F 3 "~" H 12750 6850 50 0001 C CNN
1 12750 6850
0 1 1 0
$EndComp
Wire Wire Line
12900 6850 13250 6850
Connection ~ 13250 6850
$Comp
L Device:R R3
U 1 1 5F86CB81
P 12750 7150
F 0 "R3" V 12650 7050 50 0000 C CNN
F 1 "47" V 12650 7200 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 12680 7150 50 0001 C CNN
F 3 "~" H 12750 7150 50 0001 C CNN
1 12750 7150
0 1 1 0
$EndComp
Wire Wire Line
12900 7150 13250 7150
Connection ~ 13250 7150
Text Label 12150 6400 0 50 ~ 0
AB_RED
Text Label 12150 6850 0 50 ~ 0
A_WHITE
Wire Wire Line
12150 6850 12600 6850
Text Label 12150 7150 0 50 ~ 0
A_GREEN
Wire Wire Line
12150 7150 12600 7150
$Comp
L Connector:Conn_01x02_Female SOLAR1
U 1 1 5FC3F569
P 9000 2050
F 0 "SOLAR1" H 9050 2050 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 1950 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 2050 50 0001 C CNN
F 3 "~" H 9000 2050 50 0001 C CNN
1 9000 2050
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0123
U 1 1 5FC5B972
P 8050 2150
F 0 "#PWR0123" H 8050 1900 50 0001 C CNN
F 1 "GND" H 8100 1950 50 0000 C CNN
F 2 "" H 8050 2150 50 0001 C CNN
F 3 "" H 8050 2150 50 0001 C CNN
1 8050 2150
1 0 0 -1
$EndComp
Wire Wire Line
8050 2150 8800 2150
$Comp
L Device:Net-Tie_2 NT1
U 1 1 6045DF23
P 14150 8000
F 0 "NT1" H 14150 7800 50 0000 C CNN
F 1 "Net-Tie_2" H 14150 7900 50 0000 C CNN
F 2 "NetTie:NetTie-2_THT_Pad1.0mm" H 14150 8000 50 0001 C CNN
F 3 "~" H 14150 8000 50 0001 C CNN
1 14150 8000
1 0 0 -1
$EndComp
Wire Wire Line
14250 8000 14950 8000
Connection ~ 13450 7750
$Comp
L power:VS #PWR0107
U 1 1 606E613C
P 8050 2050
F 0 "#PWR0107" H 7850 1900 50 0001 C CNN
F 1 "VS" H 8100 2250 50 0000 C CNN
F 2 "" H 8050 2050 50 0001 C CNN
F 3 "" H 8050 2050 50 0001 C CNN
1 8050 2050
1 0 0 -1
$EndComp
Wire Wire Line
13450 7750 13450 8000
Wire Wire Line
14950 7650 14950 8000
Wire Wire Line
12950 6700 13450 6700
Wire Wire Line
13450 8000 14050 8000
Connection ~ 9350 6750
$Comp
L power:GND #PWR0106
U 1 1 612B9B42
P 14950 8000
F 0 "#PWR0106" H 14950 7750 50 0001 C CNN
F 1 "GND" H 15000 7800 50 0000 C CNN
F 2 "" H 14950 8000 50 0001 C CNN
F 3 "" H 14950 8000 50 0001 C CNN
1 14950 8000
1 0 0 -1
$EndComp
Connection ~ 14950 8000
Connection ~ 13450 6700
Wire Wire Line
13450 6700 14150 6700
Connection ~ 13450 7550
Text Label 13450 8000 0 50 ~ 0
AGND
Wire Wire Line
10100 7650 10050 7650
Wire Wire Line
10100 6550 10250 6550
Wire Wire Line
8300 6750 9350 6750
$Comp
L Device:C C1
U 1 1 5FD34EBD
P 8300 7300
F 0 "C1" H 8050 7350 50 0000 L CNN
F 1 "0.1uF" H 7950 7250 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 8338 7150 50 0001 C CNN
F 3 "~" H 8300 7300 50 0001 C CNN
1 8300 7300
1 0 0 -1
$EndComp
Wire Wire Line
8300 7150 8300 6750
Wire Wire Line
8300 7450 8300 7950
Wire Wire Line
9350 7950 9550 7950
Connection ~ 9350 7950
$Comp
L power:GND #PWR0111
U 1 1 61898153
P 8300 7950
F 0 "#PWR0111" H 8300 7700 50 0001 C CNN
F 1 "GND" H 8350 7750 50 0000 C CNN
F 2 "" H 8300 7950 50 0001 C CNN
F 3 "" H 8300 7950 50 0001 C CNN
1 8300 7950
1 0 0 -1
$EndComp
Connection ~ 8300 7950
Wire Wire Line
8300 7950 9350 7950
Wire Wire Line
9350 6750 9550 6750
Wire Wire Line
10100 6750 10100 7650
Wire Wire Line
10100 6550 10100 6750
Connection ~ 10100 6750
Connection ~ 9550 6750
Wire Wire Line
9550 6750 10100 6750
Wire Wire Line
13450 6700 13450 7550
Text Label 12150 8250 0 50 ~ 0
B_WHITE
Text Label 12150 8550 0 50 ~ 0
B_GREEN
Wire Wire Line
13600 7250 12700 7250
Wire Wire Line
12700 7250 12700 8250
Wire Wire Line
12150 8250 12700 8250
Wire Wire Line
12800 7350 13600 7350
Wire Wire Line
12150 8550 12800 8550
Text Label 3300 3000 0 50 ~ 0
SCL
Text Label 3300 3100 0 50 ~ 0
SDA
Text Label 3300 3200 0 50 ~ 0
GPIO0
$Comp
L mini-beieli-pcb-cubecell-eagle-import:HTCC-AB01 HTCC-AB1
U 1 1 5F6D2856
P 3850 3950
F 0 "HTCC-AB1" H 4650 5900 50 0000 C CNN
F 1 "HTCC-AB01" H 4650 5800 50 0000 C CNN
F 2 "SUPERCAP:HTCC-AB01" V 4050 4850 50 0001 C CNN
F 3 "" V 4050 4850 50 0001 C CNN
1 3850 3950
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 5F8B4409
P 5850 2650
F 0 "#PWR0101" H 5850 2400 50 0001 C CNN
F 1 "GND" H 5900 2450 50 0000 C CNN
F 2 "" H 5850 2650 50 0001 C CNN
F 3 "" H 5850 2650 50 0001 C CNN
1 5850 2650
1 0 0 -1
$EndComp
Wire Wire Line
5850 2500 5850 2650
Text Label 3300 2800 0 50 ~ 0
VEXT
Wire Wire Line
3000 2500 3750 2500
Text Label 9350 6450 0 50 ~ 0
VEXT
Wire Wire Line
9350 6450 9350 6750
Text Label 14950 7050 0 50 ~ 0
VEXT
Wire Wire Line
14600 7050 14950 7050
Wire Wire Line
5550 2500 5850 2500
NoConn ~ 5550 2600
NoConn ~ 5550 2700
NoConn ~ 5550 2800
NoConn ~ 5550 2900
NoConn ~ 5550 3000
NoConn ~ 5550 3100
NoConn ~ 5550 3200
NoConn ~ 5550 3300
NoConn ~ 5550 3400
NoConn ~ 5550 3500
Wire Wire Line
3000 2500 3000 2900
Wire Wire Line
3300 2800 3750 2800
Wire Wire Line
3300 3000 3750 3000
Wire Wire Line
3300 3100 3750 3100
Wire Wire Line
3300 3200 3750 3200
NoConn ~ 3750 3300
NoConn ~ 3750 3400
NoConn ~ 3750 3500
Wire Wire Line
3000 2900 3750 2900
Connection ~ 3000 2900
Wire Wire Line
3000 2900 3000 3100
Wire Wire Line
5650 7400 6050 7400
Text Label 6050 7400 0 50 ~ 0
AGND
Wire Wire Line
4900 7200 5050 7200
Wire Wire Line
4900 7300 4900 7200
Wire Wire Line
6050 7300 4900 7300
Text Label 6050 7300 0 50 ~ 0
B_GREEN
Wire Wire Line
4900 7600 5050 7600
Wire Wire Line
4900 7750 4900 7600
Wire Wire Line
6050 7750 4900 7750
Text Label 6050 7750 0 50 ~ 0
B_WHITE
Wire Wire Line
5750 7600 6050 7600
Text Label 6050 7600 0 50 ~ 0
AGND
Wire Wire Line
5750 7200 6050 7200
Text Label 6050 7200 0 50 ~ 0
AB_RED
$Comp
L T4145015051-001:T4145015051-001 J2
U 1 1 602AD758
P 5350 7400
F 0 "J2" V 4850 7450 50 0000 C CNN
F 1 "T4145015051-001" V 4950 7450 50 0000 C CNN
F 2 "T4145015051-001:T4145015051-001" H 5350 7400 50 0001 L BNN
F 3 "Circular Metric Connectors; M12 R/A F PNLREAR STAMPED PIN A-CODE 5P" H 5350 7400 50 0001 L BNN
F 4 "https://www.te.com/usa-en/product-T4145015051-001.html?te_bu=Cor&te_type=disp&te_campaign=seda_glo_cor-seda-global-disp-prtnr-fy19-seda-model-bom-cta_sma-317_1&elqCampaignId=32493" H 5350 7400 50 0001 L BNN "Field4"
F 5 "TE Connectivity" H 5350 7400 50 0001 L BNN "Field5"
F 6 "Unavailable" H 5350 7400 50 0001 L BNN "Field6"
F 7 "None" H 5350 7400 50 0001 L BNN "Field7"
F 8 "T4145015051-001" H 5350 7400 50 0001 L BNN "Field8"
F 9 "T4145015051-001" H 5350 7400 50 0001 L BNN "Field9"
F 10 "None" H 5350 7400 50 0001 L BNN "Field10"
1 5350 7400
0 1 1 0
$EndComp
Wire Wire Line
3600 7400 4000 7400
Text Label 4000 7400 0 50 ~ 0
AGND
Wire Wire Line
2850 7200 3000 7200
Wire Wire Line
2850 7300 2850 7200
Wire Wire Line
4000 7300 2850 7300
Text Label 4000 7300 0 50 ~ 0
A_GREEN
Wire Wire Line
2850 7600 3000 7600
Wire Wire Line
2850 7750 2850 7600
Wire Wire Line
4000 7750 2850 7750
Text Label 4000 7750 0 50 ~ 0
A_WHITE
Wire Wire Line
3700 7600 4000 7600
Text Label 4000 7600 0 50 ~ 0
AGND
Wire Wire Line
3700 7200 4000 7200
Text Label 4000 7200 0 50 ~ 0
AB_RED
$Comp
L T4145015051-001:T4145015051-001 J1
U 1 1 601E2EC5
P 3300 7400
F 0 "J1" V 2800 7450 50 0000 C CNN
F 1 "T4145015051-001" V 2900 7450 50 0000 C CNN
F 2 "T4145015051-001:T4145015051-001" H 3300 7400 50 0001 L BNN
F 3 "Circular Metric Connectors; M12 R/A F PNLREAR STAMPED PIN A-CODE 5P" H 3300 7400 50 0001 L BNN
F 4 "https://www.te.com/usa-en/product-T4145015051-001.html?te_bu=Cor&te_type=disp&te_campaign=seda_glo_cor-seda-global-disp-prtnr-fy19-seda-model-bom-cta_sma-317_1&elqCampaignId=32493" H 3300 7400 50 0001 L BNN "Field4"
F 5 "TE Connectivity" H 3300 7400 50 0001 L BNN "Field5"
F 6 "Unavailable" H 3300 7400 50 0001 L BNN "Field6"
F 7 "None" H 3300 7400 50 0001 L BNN "Field7"
F 8 "T4145015051-001" H 3300 7400 50 0001 L BNN "Field8"
F 9 "T4145015051-001" H 3300 7400 50 0001 L BNN "Field9"
F 10 "None" H 3300 7400 50 0001 L BNN "Field10"
1 3300 7400
0 1 1 0
$EndComp
Text Notes 3500 1550 0 118 ~ 24
CubeCell (MCU/LoraWAN)
Text Notes 8000 1550 0 118 ~ 24
Connectors
Text Notes 3000 6700 0 118 ~ 24
LoadCell Connector
Text Notes 7700 6000 0 118 ~ 24
Temp/Humidity Sensor (BME280)
Text Notes 13000 6000 0 118 ~ 24
ADC (NAU7802)
Wire Wire Line
12800 8550 12800 7350
Text Label 3300 2600 0 50 ~ 0
VS
Wire Wire Line
3300 2600 3750 2600
NoConn ~ 3750 2700
$Comp
L power:PWR_FLAG #FLG0101
U 1 1 5FE71A37
P 8550 2050
F 0 "#FLG0101" H 8550 2125 50 0001 C CNN
F 1 "PWR_FLAG" H 8550 2250 50 0000 C CNN
F 2 "" H 8550 2050 50 0001 C CNN
F 3 "~" H 8550 2050 50 0001 C CNN
1 8550 2050
1 0 0 -1
$EndComp
Connection ~ 8550 2050
Wire Wire Line
8550 2050 8800 2050
Wire Wire Line
8050 2050 8550 2050
Text Notes 8000 1750 0 50 ~ 0
5.5V - 7V
$Comp
L Connector:Conn_01x02_Female SWITCH1
U 1 1 5FE8083E
P 9000 2800
F 0 "SWITCH1" H 9050 2800 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 2700 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 2800 50 0001 C CNN
F 3 "~" H 9000 2800 50 0001 C CNN
1 9000 2800
1 0 0 -1
$EndComp
Wire Wire Line
8050 2900 8800 2900
$Comp
L Connector:Conn_01x02_Female LIPO1
U 1 1 5FE8567F
P 9000 3500
F 0 "LIPO1" H 9050 3500 50 0000 L CNN
F 1 "Conn_01x02_Female" H 9050 3400 50 0000 L CNN
F 2 "Connector_JST:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical" H 9000 3500 50 0001 C CNN
F 3 "~" H 9000 3500 50 0001 C CNN
1 9000 3500
1 0 0 -1
$EndComp
Wire Wire Line
8050 3600 8800 3600
Wire Wire Line
8050 3500 8800 3500
$Comp
L Connector_Generic:Conn_01x02 J3
U 1 1 5FEA044E
P 9200 4300
F 0 "J3" H 9300 4300 50 0000 L CNN
F 1 "Conn_01x02" H 9300 4200 50 0000 L CNN
F 2 "Connector_Wire:SolderWire-0.1sqmm_1x02_P3.6mm_D0.4mm_OD1mm" H 9200 4300 50 0001 C CNN
F 3 "~" H 9200 4300 50 0001 C CNN
1 9200 4300
1 0 0 -1
$EndComp
Text Notes 8900 3450 0 50 ~ 0
+
$Comp
L power:GND #PWR?
U 1 1 5FEAB739
P 8050 3600
F 0 "#PWR?" H 8050 3350 50 0001 C CNN
F 1 "GND" H 8100 3400 50 0000 C CNN
F 2 "" H 8050 3600 50 0001 C CNN
F 3 "" H 8050 3600 50 0001 C CNN
1 8050 3600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5FEB0754
P 9000 4400
F 0 "#PWR?" H 9000 4150 50 0001 C CNN
F 1 "GND" H 9050 4200 50 0000 C CNN
F 2 "" H 9000 4400 50 0001 C CNN
F 3 "" H 9000 4400 50 0001 C CNN
1 9000 4400
1 0 0 -1
$EndComp
Text Notes 9000 4250 0 50 ~ 0
+
Wire Wire Line
9000 4300 7600 4300
Wire Wire Line
7600 4300 7600 2800
Wire Wire Line
7600 2800 8800 2800
Wire Wire Line
8050 2900 8050 3500
$EndSCHEMATC

View File

@ -0,0 +1,33 @@
(page_layout
(setup (textsize 1.5 1.5)(linewidth 0.15)(textlinewidth 0.15)
(left_margin 10)(right_margin 10)(top_margin 10)(bottom_margin 10))
(rect (name rect1:Rect) (start 110 34) (end 2 2))
(rect (name rect2:Rect) (start 0 0 ltcorner) (end 0 0) (repeat 2) (incrx 2) (incry 2))
(line (name segm1:Line) (start 50 2 ltcorner) (end 50 0 ltcorner) (repeat 30) (incrx 50))
(tbtext 1 (name text1:Text) (pos 25 1 ltcorner) (font (size 1.3 1.3)) (repeat 100) (incrx 50))
(line (name segm2:Line) (start 50 2 lbcorner) (end 50 0 lbcorner) (repeat 30) (incrx 50))
(tbtext 1 (name text2:Text) (pos 25 1 lbcorner) (font (size 1.3 1.3)) (repeat 100) (incrx 50))
(line (name segm3:Line) (start 0 50 ltcorner) (end 2 50 ltcorner) (repeat 30) (incry 50))
(tbtext A (name text3:Text) (pos 1 25 ltcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
(line (name segm4:Line) (start 0 50 rtcorner) (end 2 50 rtcorner) (repeat 30) (incry 50))
(tbtext A (name text4:Text) (pos 1 25 rtcorner) (font (size 1.3 1.3)) (justify center) (repeat 100) (incry 50))
(tbtext "Date: %D" (name text5:Text) (pos 87 6.9))
(line (name segm5:Line) (start 110 5.5) (end 2 5.5))
(tbtext %K (name text6:Text) (pos 109 4.1))
(line (name segm6:Line) (start 110 8.5) (end 2 8.5))
(tbtext "Rev: %R" (name text7:Text) (pos 24 6.9) (font bold))
(tbtext "Size: %Z" (name text8:Text) (pos 109 6.9))
(tbtext "Id: %S/%N" (name text9:Text) (pos 24 4.1))
(line (name segm7:Line) (start 110 12.5) (end 2 12.5))
(tbtext "Title: %T" (name text10:Text) (pos 109 10.7) (font (size 2 2) bold italic))
(tbtext "File: %F" (name text11:Text) (pos 109 14.3))
(line (name segm8:Line) (start 110 18.5) (end 2 18.5))
(tbtext "Sheet: %P" (name text12:Text) (pos 109 17))
(tbtext %Y (name text13:Text) (pos 109 20) (font bold))
(tbtext %C0 (name text14:Text) (pos 109 23))
(tbtext %C1 (name text15:Text) (pos 109 26))
(tbtext %C2 (name text16:Text) (pos 109 29))
(tbtext %C3 (name text17:Text) (pos 109 32))
(line (name segm9:Line) (start 90 8.5) (end 90 5.5))
(line (name segm10:Line) (start 26 8.5) (end 26 2))
)

View File

@ -0,0 +1,34 @@
(module SOIC127P700X210-16N (layer F.Cu) (tedit 5EA843BF)
(fp_text reference REF** (at 0.175 -6.435) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.015)))
)
(fp_text value SOIC127P700X210-16N (at 8.765 6.365) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.015)))
)
(fp_circle (center -1.6 -4.4) (end -1.4 -4.4) (layer F.SilkS) (width 0.3))
(fp_line (start -4.375 5.5) (end -4.375 -5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.375 5.5) (end -4.375 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.375 -5.5) (end 4.375 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.375 -5.5) (end 4.375 -5.5) (layer F.CrtYd) (width 0.05))
(fp_circle (center -3.2 -5.4) (end -3.1 -5.4) (layer F.SilkS) (width 0.2))
(fp_line (start -2.2 5.15) (end -2.2 -5.15) (layer F.Fab) (width 0.2))
(fp_line (start 2.2 5.15) (end -2.2 5.15) (layer F.SilkS) (width 0.2))
(fp_line (start 2.2 -5.15) (end 2.2 5.15) (layer F.Fab) (width 0.2))
(fp_line (start -2.2 -5.15) (end 2.2 -5.15) (layer F.SilkS) (width 0.2))
(pad 16 smd rect (at 3.105 -4.445) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 3.105 -3.175) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 3.105 -1.905) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 3.105 -0.635) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 3.105 0.635) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 3.105 1.905) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 3.105 3.175) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at 3.105 4.445) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -3.105 4.445) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -3.105 3.175) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -3.105 1.905) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -3.105 0.635) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -3.105 -0.635) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -3.105 -1.905) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -3.105 -3.175) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at -3.105 -4.445) (size 1.8 0.64) (layers F.Cu F.Paste F.Mask))
)

View File

@ -0,0 +1,6 @@
(sym_lib_table
(version 7)
(lib (name "mini-beieli-pcb-cubecell-eagle-import")(type "Legacy")(uri "${KIPRJMOD}/mini-beieli-pcb-cubecell-eagle-import.lib")(options "")(descr ""))
(lib (name "mini-beieli-pcb-cubecell-rescue")(type "KiCad")(uri "${KIPRJMOD}/mini-beieli-pcb-cubecell-rescue.kicad_sym")(options "")(descr ""))
(lib (name "T4145015051-001")(type "Legacy")(uri "/home/joerg/git-repos/mini-beieli-pcb-cubecell/kicad-files/T4145015051-001/T4145015051-001.lib")(options "")(descr ""))
)

View File

@ -0,0 +1 @@
{"hostname":"mbp","username":"joerg"}