merge conflicting files

kicad-files/T4145015051-001/License.txt

@@ -0,0 +1,24 @@
+BY ACCESSING OR USING THESE SYMBOLS & FOOTPRINTS ("MODELS"), YOU ARE ACKNOWLEDGING THAT YOU HAVE READ, FULLY UNDERSTAND AND AGREE TO THESE TERMS AND CONDITIONS (the "Agreement"), WHICH CONSTITUTE A BINDING AGREEMENT BETWEEN YOU AND SNAPEDA, INC., ENTERED INTO ON THE DATE OF SUCH OCCURRENCE (the "Effective Date"). IF YOU ARE ACCESSING OR USING THESE FILES ON BEHALF OF AN ENTITY, YOU REPRESENT THAT YOU HAVE THE RIGHT, AUTHORITY, AND CAPACITY TO BIND SUCH ENTITY TO THIS AGREEMENT AND HEREBY DO SO. IF YOU DO NOT AGREE WITH ANY OF THE TERMS OR CONDITIONS OF THIS AGREEMENT, YOU MUST NOT USE ANY PART OF THESE MODELS.
+
+1. Design License
+
+You and your sub-licensees are hereby licensed to design, manufacture, use and distribute, circuit board designs and circuit boards formed by combining Models provided by SnapEDA with other circuit elements of your choosing. You may then convey such combinations under licensing terms of your choice. 
+
+Individual Models remain the intellectual property of SnapEDA, Inc. You shall not (and shall not permit or encourage any third party to) to do any of the following :
+
+(a) sell, assign, lease, lend, rent, issue, sublicense, make available, or otherwise distribute to any third party, or publicly perform, display or communicate, the Models (for example, by uploading Models to another website or software application);

+(b) remove, alter, or conceal, any copyright, trademark, or other proprietary rights notice or legend displayed or contained in the individual Models.
+
+For further clarity, once integrated into a schematic design or PCB layout, Models may be modified freely for the purpose of designing a circuit board. 
+
+
+2. Limitation of Liability
+
+IN NO EVENT WILL SNAPEDA, TE CONNECTIVITY, OR OUR SUBSIDIARIES, AGENTS, SUCCESSORS, THIRD PARTY PROVIDERS, AND/OR ANY OF THE FOREGOING ENTITIES' RESPECTIVE DIRECTORS, OFFICERS, EMPLOYEES, AGENTS, REPRESENTATIVES, CUSTOMERS, SUPPLIERS, OR LICENSORS BE RESPONSIBLE OR LIABLE UNDER, OR OTHERWISE IN CONNECTION WITH THIS AGREEMENT, FOR:
+
+(a) ANY CONSEQUENTIAL, INDIRECT, SPECIAL, INCIDENTAL, OR PUNITIVE DAMAGES;
+(b) ANY LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF REVENUE, OR LOSS OF ANTICIPATED SAVINGS;
+(c) ANY LOSS OF, OR DAMAGE TO, DATA, REPUTATION, OR GOODWILL; AND/OR
+(d) THE COST OF PROCURING ANY SUBSTITUTE GOODS OR SERVICES.
+
+THE COMBINED AGGREGATE LIABILITY OF SNAPEDA AND ALL SNAPEDA CONTENT AFFILIATES UNDER, OR OTHERWISE IN CONNECTION WITH, THIS AGREEMENT SHALL NOT EXCEED THE TOTAL AMOUNT OF FEES RECEIVED BY SNAPEDA FROM YOU IN THE PREVIOUS TWELVE (12) MONTHS. THE FOREGOING EXCLUSIONS AND LIMITATIONS SHALL APPLY: (a) EVEN IF SNAPEDA OR ANY SNAPEDA CONTENT AFFILIATE HAS BEEN ADVISED, OR SHOULD HAVE BEEN AWARE, OF THE POSSIBILITY OF LOSSES, DAMAGES, OR COSTS; (b) EVEN IF ANY REMEDY IN THIS AGREEMENT FAILS OF ITS ESSENTIAL PURPOSE; AND (c) REGARDLESS OF THE THEORY OR BASIS OF LIABILITY (INCLUDING WITHOUT LIMITATION BREACH OF CONTRACT, TORT, NEGLIGENCE, AND STRICT LIABILITY).

kicad-files/T4145015051-001/T4145015051-001.kicad_mod

@@ -0,0 +1,23 @@
+
+(module T4145015051-001 (layer F.Cu) (tedit 5FECA2F1)
+  (descr "")
+  (fp_text reference REF** (at -7.40839 -6.85962 0) (layer F.SilkS)
+    (effects (font (size 0.787952755906 0.787952755906) (thickness 0.015)))
+  )
+  (fp_text value T4145015051-001 (at -2.374505 7.252835 0) (layer F.Fab)
+    (effects (font (size 0.788590551181 0.788590551181) (thickness 0.015)))
+  )
+  (fp_line (start 9.65 6.55) (end -9.85 6.55) (layer F.SilkS) (width 0.127))
+  (fp_line (start -9.85 6.55) (end -9.85 -5.5) (layer F.SilkS) (width 0.127))
+  (fp_line (start -9.85 -5.5) (end 9.65 -5.5) (layer F.SilkS) (width 0.127))
+  (fp_line (start 9.65 -5.5) (end 9.65 6.55) (layer F.SilkS) (width 0.127))
+  (pad P$1 thru_hole circle (at -1.77 -1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
+  (pad P$2 thru_hole circle (at 1.77 -1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
+  (pad P$3 thru_hole circle (at -1.77 1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
+  (pad P$4 thru_hole circle (at 1.77 1.77) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
+  (pad P$5 thru_hole circle (at 0.0 0.0) (size 2.0 2.0) (drill 1.4) (layers *.Cu *.Mask))
+  (pad None np_thru_hole circle (at 7.5 0.0) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
+  (pad None np_thru_hole circle (at 7.5 4.0) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
+  (pad None np_thru_hole circle (at -7.5 0.0) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
+  (pad None np_thru_hole circle (at -7.5 4.0) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask))
+)

kicad-files/T4145015051-001/T4145015051-001.lib

@@ -0,0 +1,30 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#(c) SnapEDA 2016 (snapeda.com)
+#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
+#
+# T4145015051-001
+#
+DEF T4145015051-001 J 0 40 N Y 1 L N
+F0 "J" -300 500 50 H V L BNN
+F1 "T4145015051-001" -300 -500 50 H V L BNN
+F2 "T4145015051-001" 0 0 50 H I L BNN
+F3 "" 0 0 50 H I L BNN
+DRAW
+P 2 0 0 10 -300 400 -300 -300 N
+P 2 0 0 10 -300 -300 300 -300 N
+P 2 0 0 10 300 -300 300 400 N
+P 2 0 0 10 -300 400 -100 400 N
+P 2 0 0 10 -100 400 -100 300 N
+P 2 0 0 10 -100 300 100 300 N
+P 2 0 0 10 100 300 100 400 N
+P 2 0 0 10 100 400 300 400 N
+X 5 P$5 0 300 300 D 40 40 0 0 B I
+X 2 P$2 200 400 200 D 40 40 0 0 B I
+X 1 P$1 -200 400 200 D 40 40 0 0 B I
+X 3 P$3 200 -300 200 U 40 40 0 0 B I
+X 4 P$4 -200 -300 200 U 40 40 0 0 B I
+ENDDRAW
+ENDDEF
+#
+# End Library

kicad-files/T4145015051-001/how-to-import.htm

@@ -0,0 +1 @@
+<!DOCTYPE HTML><html lang="en-US"> <head> <meta charset="UTF-8"> <meta http-equiv="refresh" content="0; url=https://www.snapeda.com/te/#"> <script type="text/javascript">window.location.href="https://www.snapeda.com/te/#" </script> <title>Page Redirection</title> </head> <body> If you are not redirected automatically, follow this <a href="https://www.snapeda.com/te/#">link to the import guide</a>. </body></html>

kicad-files/mini-beieli-pcb-cubecell-cache.lib

@@ -21,17 +21,26 @@ X Pin_2 2 -200 -100 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+<<<<<<< HEAD
 # Connector_Conn_01x03_Male
 #
 DEF Connector_Conn_01x03_Male J 0 40 Y N 1 F N
 F0 "J" 0 200 50 H V C CNN
 F1 "Connector_Conn_01x03_Male" 0 -200 50 H V C CNN
+=======
+# Connector_Generic_Conn_01x02
+#
+DEF Connector_Generic_Conn_01x02 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Connector_Generic_Conn_01x02" 0 -200 50 H V C CNN
+>>>>>>> new-master-imported-5.1-in-kicad8
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
  Connector*:*_1x??_*
 $ENDFPLIST
 DRAW
+<<<<<<< HEAD
 S 34 -95 0 -105 1 1 6 F
 S 34 5 0 -5 1 1 6 F
 S 34 105 0 95 1 1 6 F
@@ -41,6 +50,13 @@ P 2 1 1 6 50 100 34 100 N
 X Pin_1 1 200 100 150 L 50 50 1 1 P
 X Pin_2 2 200 0 150 L 50 50 1 1 P
 X Pin_3 3 200 -100 150 L 50 50 1 1 P
+=======
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+>>>>>>> new-master-imported-5.1-in-kicad8
 ENDDRAW
 ENDDEF
 #
@@ -62,26 +78,6 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_CP
-#
-DEF Device_CP C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "Device_CP" 25 -100 50 H V L CNN
-F2 "" 38 -150 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- CP_*
-$ENDFPLIST
-DRAW
-S -90 20 90 40 0 1 0 N
-S 90 -20 -90 -40 0 1 0 F
-P 2 0 1 0 -70 90 -30 90 N
-P 2 0 1 0 -50 110 -50 70 N
-X ~ 1 0 150 110 D 50 50 1 1 P
-X ~ 2 0 -150 110 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
 # Device_Net-Tie_2
 #
 DEF Device_Net-Tie_2 NT 0 0 N N 1 F N
@@ -116,6 +112,7 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+<<<<<<< HEAD
 # Qwiic_Scale-eagle-import_NAU7802SOIC
 #
 DEF Qwiic_Scale-eagle-import_NAU7802SOIC U 0 40 Y Y 1 L N
@@ -134,7 +131,7 @@ X XOUT 11 500 -200 100 L 0 50 1 0 B
 X DRDY 12 500 -100 100 L 0 50 1 0 B
 X SCLK 13 500 0 100 L 0 50 1 0 B
 X SDIO 14 500 100 100 L 0 50 1 0 B
-X DVDD 15 500 200 100 L 0 50 1 0 B
+X DVDD 15 500 200 100 L 0 50 1 0 W
 X AVDD 16 500 300 100 L 0 50 1 0 B
 X VIN1N 2 -500 200 100 R 0 50 1 0 B
 X VIN1P 3 -500 100 100 R 0 50 1 0 B
@@ -143,10 +140,12 @@ X VIN2P 5 -500 -100 100 R 0 50 1 0 B
 X VBG 6 -500 -200 100 R 0 50 1 0 B
 X REFN 7 -500 -300 100 R 0 50 1 0 B
 X AVSS 8 -500 -400 100 R 0 50 1 0 B
-X DVSS 9 500 -400 100 L 0 50 1 0 B
+X DVSS 9 500 -400 100 L 0 50 1 0 W
 ENDDRAW
 ENDDEF
 #
+=======
+>>>>>>> new-master-imported-5.1-in-kicad8
 # Sensor_BME280
 #
 DEF Sensor_BME280 U 0 20 Y Y 1 F N
@@ -193,14 +192,7 @@ DEF T4145015051-001_T4145015051-001 J 0 40 N Y 1 L N
 F0 "J" -300 500 50 H V L BNN
 F1 "T4145015051-001_T4145015051-001" -300 -500 50 H V L BNN
 F2 "T4145015051-001" 0 0 50 H I L BNN
-F3 "Circular Metric Connectors; M12 R/A F PNLREAR STAMPED PIN A-CODE 5P" 0 0 50 H I L BNN
+F3 "" 0 0 50 H I L BNN
-F4 "https://www.te.com/usa-en/product-T4145015051-001.html?te_bu=Cor&te_type=disp&te_campaign=seda_glo_cor-seda-global-disp-prtnr-fy19-seda-model-bom-cta_sma-317_1&elqCampaignId=32493" 0 0 50 H I L BNN
-F5 "TE Connectivity" 0 0 50 H I L BNN
-F6 "Unavailable" 0 0 50 H I L BNN
-F7 "None" 0 0 50 H I L BNN
-F8 "T4145015051-001" 0 0 50 H I L BNN
-F9 "T4145015051-001" 0 0 50 H I L BNN
-F10 "None" 0 0 50 H I L BNN
 DRAW
 P 2 0 0 10 -300 -300 300 -300 N
 P 2 0 0 10 -300 400 -300 -300 N
@@ -218,6 +210,7 @@ X 5 P$5 0 300 300 D 40 40 0 0 B I
 ENDDRAW
 ENDDEF
 #
+<<<<<<< HEAD
 # Transistor_FET_AO3401A
 #
 DEF Transistor_FET_AO3401A Q 0 20 Y N 1 F N
@@ -329,6 +322,9 @@ ENDDRAW
 ENDDEF
 #
 # mini-beieli-pcb-cubecell-eagle-import_HTCC-AM01
+=======
+# mini-beieli-pcb-cubecell-eagle-import_HTCC-AB01
+>>>>>>> new-master-imported-5.1-in-kicad8
 #
 DEF mini-beieli-pcb-cubecell-eagle-import_HTCC-AM01 U? 0 40 Y Y 1 F N
 F0 "U?" -1150 1300 50 H V C CNN
@@ -362,45 +358,34 @@ X TX 9 -200 900 100 D 50 50 0 0 O
 ENDDRAW
 ENDDEF
 #
-# mini-beieli-pcb-cubecell-eagle-import_L0603_10UH
+# mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import
 #
-DEF mini-beieli-pcb-cubecell-eagle-import_L0603_10UH L 0 40 Y Y 1 L N
+DEF mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import U 0 40 Y Y 1 L N
-F0 "L" 150 -200 59 V V L BNN
+F0 "U" -400 430 70 H V L BNN
-F1 "mini-beieli-pcb-cubecell-eagle-import_L0603_10UH" -50 -200 59 V V L BNN
+F1 "mini-beieli-pcb-cubecell-rescue_NAU7802SOIC-Qwiic_Scale-eagle-import" -400 -600 70 H V L BNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 DRAW
-A 0 -150 50 0 900 1 0 10 N 50 -150 0 -100
+P 2 1 0 0 -400 -500 -400 400 N
-A 0 -150 50 -900 0 1 0 10 N 0 -200 50 -150
+P 2 1 0 0 -400 400 400 400 N
-A 0 -50 50 0 900 1 0 10 N 50 -50 0 0
+P 2 1 0 0 400 -500 -400 -500 N
-A 0 -50 50 -900 0 1 0 10 N 0 -100 50 -50
+P 2 1 0 0 400 400 400 -500 N
-A 0 50 50 0 900 1 0 10 N 50 50 0 100
+X REFP 1 -500 300 100 R 0 50 1 0 B
-A 0 50 50 -900 0 1 0 10 N 0 0 50 50
+X XIN 10 500 -300 100 L 0 50 1 0 B
-A 0 150 50 0 900 1 0 10 N 50 150 0 200
+X XOUT 11 500 -200 100 L 0 50 1 0 B
-A 0 150 50 -900 0 1 0 10 N 0 100 50 150
+X DRDY 12 500 -100 100 L 0 50 1 0 B
-X 1 1 0 300 100 D 0 0 1 0 P
+X SCLK 13 500 0 100 L 0 50 1 0 B
-X 2 2 0 -300 100 U 0 0 1 0 P
+X SDIO 14 500 100 100 L 0 50 1 0 B
-ENDDRAW
+X DVDD 15 500 200 100 L 0 50 1 0 B
-ENDDEF
+X AVDD 16 500 300 100 L 0 50 1 0 B
-#
+X VIN1N 2 -500 200 100 R 0 50 1 0 B
-# mini-beieli-pcb-cubecell-eagle-import_L3.9X3.9_10UH_0.55A
+X VIN1P 3 -500 100 100 R 0 50 1 0 B
-#
+X VIN2N 4 -500 0 100 R 0 50 1 0 B
-DEF mini-beieli-pcb-cubecell-eagle-import_L3.9X3.9_10UH_0.55A L 0 40 Y Y 1 L N
+X VIN2P 5 -500 -100 100 R 0 50 1 0 B
-F0 "L" 150 -200 59 V V L BNN
+X VBG 6 -500 -200 100 R 0 50 1 0 B
-F1 "mini-beieli-pcb-cubecell-eagle-import_L3.9X3.9_10UH_0.55A" -50 -200 59 V V L BNN
+X REFN 7 -500 -300 100 R 0 50 1 0 B
-F2 "" 0 0 50 H I C CNN
+X AVSS 8 -500 -400 100 R 0 50 1 0 B
-F3 "" 0 0 50 H I C CNN
+X DVSS 9 500 -400 100 L 0 50 1 0 B
-DRAW
-A 0 -150 50 0 900 1 0 10 N 50 -150 0 -100
-A 0 -150 50 -900 0 1 0 10 N 0 -200 50 -150
-A 0 -50 50 0 900 1 0 10 N 50 -50 0 0
-A 0 -50 50 -900 0 1 0 10 N 0 -100 50 -50
-A 0 50 50 0 900 1 0 10 N 50 50 0 100
-A 0 50 50 -900 0 1 0 10 N 0 0 50 50
-A 0 150 50 0 900 1 0 10 N 50 150 0 200
-A 0 150 50 -900 0 1 0 10 N 0 100 50 150
-X 1 1 0 300 100 D 0 0 1 0 P
-X 2 2 0 -300 100 U 0 0 1 0 P
 ENDDRAW
 ENDDEF
 #

kicad-files/mini-beieli-pcb-cubecell-rescue.dcm

@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library

kicad-files/mini-beieli-pcb-cubecell-rescue.lib

@@ -0,0 +1,35 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# NAU7802SOIC-Qwiic_Scale-eagle-import
+#
+DEF NAU7802SOIC-Qwiic_Scale-eagle-import U 0 40 Y Y 1 L N
+F0 "U" -400 430 70 H V L BNN
+F1 "NAU7802SOIC-Qwiic_Scale-eagle-import" -400 -600 70 H V L BNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 1 0 0 -400 -500 -400 400 N
+P 2 1 0 0 -400 400 400 400 N
+P 2 1 0 0 400 -500 -400 -500 N
+P 2 1 0 0 400 400 400 -500 N
+X REFP 1 -500 300 100 R 0 50 1 0 B
+X XIN 10 500 -300 100 L 0 50 1 0 B
+X XOUT 11 500 -200 100 L 0 50 1 0 B
+X DRDY 12 500 -100 100 L 0 50 1 0 B
+X SCLK 13 500 0 100 L 0 50 1 0 B
+X SDIO 14 500 100 100 L 0 50 1 0 B
+X DVDD 15 500 200 100 L 0 50 1 0 B
+X AVDD 16 500 300 100 L 0 50 1 0 B
+X VIN1N 2 -500 200 100 R 0 50 1 0 B
+X VIN1P 3 -500 100 100 R 0 50 1 0 B
+X VIN2N 4 -500 0 100 R 0 50 1 0 B
+X VIN2P 5 -500 -100 100 R 0 50 1 0 B
+X VBG 6 -500 -200 100 R 0 50 1 0 B
+X REFN 7 -500 -300 100 R 0 50 1 0 B
+X AVSS 8 -500 -400 100 R 0 50 1 0 B
+X DVSS 9 500 -400 100 L 0 50 1 0 B
+ENDDRAW
+ENDDEF
+#
+#End Library

kicad-files/mini-beieli-pcb-cubecell.kicad_prl

@@ -0,0 +1,83 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "All Layers",
+    "auto_track_width": true,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": false,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
+      0,
+      1,
+      2,
+      3,
+      4,
+      5,
+      8,
+      9,
+      10,
+      11,
+      12,
+      13,
+      15,
+      16,
+      17,
+      18,
+      19,
+      20,
+      21,
+      22,
+      23,
+      24,
+      25,
+      26,
+      27,
+      28,
+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36,
+      39,
+      40
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "git": {
+    "repo_password": "",
+    "repo_type": "",
+    "repo_username": "",
+    "ssh_key": ""
+  },
+  "meta": {
+    "filename": "mini-beieli-pcb-cubecell.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": []
+  }
+}

kicad-files/mini-beieli-pcb-cubecell.kicad_pro

@@ -0,0 +1,359 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "apply_defaults_to_fp_fields": false,
+        "apply_defaults_to_fp_shapes": false,
+        "apply_defaults_to_fp_text": false,
+        "board_outline_line_width": 0.05,
+        "copper_line_width": 0.2,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.05,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.1,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.1,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.12,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "min_clearance": 0.508
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "filename": "board_design_settings.json",
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_symbol_mismatch": "warning",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "holes_co_located": "warning",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "warning",
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+      "internal_id": "",
+      "mfg": "",
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+    "viewports": []
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+  "cvpcb": {
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+  },
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kicad-files/mini-beieli-pcb-cubecell.pro

@@ -1,4 +1,4 @@
-update=Sa 05 Sep 2020 11:51:39
+update=Mo 14 Dez 2020 16:52:19
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kicad-files/sym-lib-table

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+  (lib (name mini-beieli-pcb-cubecell-rescue)(type Legacy)(uri ${KIPRJMOD}/mini-beieli-pcb-cubecell-rescue.lib)(options "")(descr ""))
+  (lib (name T4145015051-001)(type Legacy)(uri /home/joerg/git-repos/mini-beieli-pcb-cubecell/kicad-files/T4145015051-001/T4145015051-001.lib)(options "")(descr ""))
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pcbway-5.0/gerber/mini-beieli-pcb-cubecell-NPTH.drl

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pcbway-5.0/gerber/mini-beieli-pcb-cubecell-all.pos

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+### Module positions - created on Sat Dec 26 11:22:16 2020 ###
+### Printed by Pcbnew version kicad 5.1.8-5.fc33
+## Unit = mm, Angle = deg.
+## Side : All
+# Ref     Val       Package                                                   PosX       PosY       Rot  Side
+C1        0.1uF     C_0603_1608Metric                                      51.9160    21.6330    0.0000  top
+C2        0.1uF     C_0603_1608Metric                                     100.4620    18.8550    0.0000  top
+C3        1uF       C_0603_1608Metric                                      93.0960    18.6010    0.0000  top
+C4        0.1uF     C_0603_1608Metric                                     100.4620    22.4110    0.0000  top
+C5        0.1uF     C_0603_1608Metric                                     100.4620    29.7770    0.0000  top
+R1        10k       R_0603_1608Metric                                      51.9160    19.1230    0.0000  top
+R2        47        R_0603_1608Metric                                     100.4620    20.6330    0.0000  top
+R3        47        R_0603_1608Metric                                     100.4620    24.1890    0.0000  top
+U1        BME280    Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering    47.8520    20.1090   90.0000  top
+## End

pcbway-5.1/gerber/mini-beieli-pcb-cubecell-B_Mask.gbs

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pcbway-5.1/gerber/mini-beieli-pcb-cubecell-B_SilkS.gbo

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pcbway-5.1/gerber/mini-beieli-pcb-cubecell-Edge_Cuts.gm1

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pcbway-5.1/gerber/mini-beieli-pcb-cubecell-NPTH.drl

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pcbway-5.1/gerber/mini-beieli-pcb-cubecell-PTH.drl

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pcbway-5.1/mini-beieli-pcb-cubecell-all.pos

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+### Module positions - created on Sat Dec 26 13:44:04 2020 ###
+### Printed by Pcbnew version kicad 5.1.8-5.fc33
+## Unit = mm, Angle = deg.
+## Side : All
+# Ref     Val       Package                                                   PosX       PosY       Rot  Side
+C1        0.1uF     C_0603_1608Metric                                      51.9160    21.6330    0.0000  top
+C2        0.1uF     C_0603_1608Metric                                     100.4620    18.8550    0.0000  top
+C3        1uF       C_0603_1608Metric                                      93.0960    18.6010    0.0000  top
+C4        0.1uF     C_0603_1608Metric                                     100.4620    22.4110    0.0000  top
+C5        0.1uF     C_0603_1608Metric                                     100.4620    29.7770    0.0000  top
+R1        10k       R_0603_1608Metric                                      51.9160    19.1230    0.0000  top
+R2        47        R_0603_1608Metric                                     100.4620    20.6330    0.0000  top
+R3        47        R_0603_1608Metric                                     100.4620    24.1890    0.0000  top
+U1        BME280    Bosch_LGA-8_2.5x2.5mm_P0.65mm_ClockwisePinNumbering    47.8520    20.1090   90.0000  top
+## End